Research On Loop Pipelining Optimization Technology In Reconfigurable Compiling

With the development of semiconductor technology,the reconfigurable computing architecture which is based on multidimensional calculation method about space-time,has broken through the limitations of the Von Neumann architecture.Due to both flexibility of general processors and efficiency of ASIC(application-specific integrated circuit)chips,the reconfigurable computing is widely used in important areas such as high-performance computing,digital signal processing,network information security,and becoming another way of mainstream computing.The latent value of reconfigurable computing is gradually attentioned by people in business and technology.For general computing,the reconfigurable computing based on heterogeneous architecture about GPP+FPGA,is superior to the general processor with traditional architecture in energy consumption,storage resources and performance.This makes the reconfigurable computing becoming an important research direction in the future of computing.Due for the research of reconfigurable computing both in it's infancy,although there have been a lot of achievements,but there are still many problems need to be resolved in the future.Because of the immaturity software ecosystem related to reconfigurable computing system and without limited by semiconductor manufacturing process or hardware technology,the technology of reconfigurable compiler for reconfigurable computing becomes the focus and hot spot around the world at present.Through analysising the features of hardware acceleration for general applications in reconfigurable computing systems,the improving of automatic mapping technology for iteration structure in application to the parallel pipelining hardware accelerator in reconfigurable systems has become an attentional subject in this field.As the research foundation of existing research results,this paper has mainly researched the automatic mapping and optimization technology about loop program,include operation unit,control unit and memory unit.In this thesis,the concrete research content is as follows:(1)In the existing reconfigurable compiler,when the loop program is mapping to pipelined computing unit automatically,the directed dividing method is often used,without considering the real hardware delay of basic instructions and generating the improvable pipelining result.For this kind of situation,an automatic pipelining and scheduling algorithm based on the hardware delay characteristics is proposed.Based on the hardware delay characteristics for basic operation instructions in FPGAs,the library of basic instruction hardware delay is established.Then the node of operator is scheduled according to the hardware delay and the pipelined is optimized automatically.Experimental results manifest that the proposed algorithm can reduce pipeline segments number effectively,to reduce the overhead register resource caused by pipelining.At the same time,this method can reduce the number of clock cycles of single iteration excecuting.(2)When the loop is executed pipelining,the initiation interval between iterations is controlled by guidance statements in existing reconfigurable compilers.But this method can only generate the fixed initiation interval,and can not increase the performance of pipelining.At the same time,the automation of reconfigurable compiler has been limited.Aimed at this problem,an automatic analysis and optimization about initiation interval for loop pipeline is proposed in this thesis.Based on the none-fixed initiation interval control strategy,the loop pipeline initiation interval information model is established.The automatic analysis algorithm about initiation interval is designed and implemented,and the initiation interval is optimized by pipelinine scheduling technology.Experimental results show that the none-fixed initiation interval control strategy,proposed in this thesis,can effectively reduce the waiting time between iterations for loop pipelining.By this automatic algorithm,the automation of reconfigurable compiler can be improved efficiently.(3)There have been a lot of research archievements about parallel memory structure in existing reconfigurable compilers.Many of them tend to adopt the strategy of trading space for time in order to improve the parallelism and reuse of data.However,there are many spaces for improvement in the resources and performance.For this kind of situation,a method of automatic mapping for parameterized parallelism memory architecture is proposed for affine subscript arrays in iteration.A parallelism memory architecture is designed.Then the memory structure is generated finally by building the memory data dependence graph automatically and calculating the parameter values.Experimental results show that the proposed memory architecture can fully mine the data parallelism and reuse.Compared with the existing solutions,this architecture can improve the performance of loop pipelining with less hardware resources.Finally,combined with the above research content,an automatically mapping framework for loop pipelining is established for reconfigurable compiler.When the operation units,control unit,and memory units of loop programs are generated automatically for reconfigurable computing systems,the above methods are used and implemented respectively,includes automatic pipelining and scheduling algorithm,automatic analysis and optimization about initiation interval for loop pipeline and method of automatic mapping for parameterized parallelism memory architecture.The experimental results show that this method proposed by this thesis can improve the automation level for reconfigurable compiler and performance of loop pipelining for reconfirguable computing systems,and is certain feasibility.