Research Of Image Parallel Registration Technology Based On General Reconfigurable Processor

The rapid development of image processing technology and multimedia technology puts forwards higher requirements for the amount of data needed to deal with, computation complexity and real-time processing. With the existing hardware structure of which general processor and application-specific integrated circuit are as the main computing architecture, it is difficult to meet these requirements on computational efficiency and computational flexibility at the same time. Processing unit array structure of the reconfigurable processor has a characteristic of flexible configuration of repeatable, which can be widely applicable to different types of algorithm. The structure also has a computing characteristic of high parallelism, which can help efficiently completing complex computations of large amounts of data, improving algorithm's execution efficiency greatly. All of these make reconfigurable processor significant suitable for the processing of image registration algorithm.Based on the general reconfigurable processor, this paper deeply analyzes the mapping methods of key loop bodies on the processing unit array, including data flow dismantling of the algorithm hotspots before the mapping, implementation method based on temporal mapping and parallel pipelining method based on spatial mapping. Then we conduct serial computing analysis of image registration and processing algorithm which includes normalized cross correlation, random sample consensus and two-dimension discrete cosine transform. Based on 3 principles that the size of the configuration information, the frequency of the processor reconfiguration and time delay of data transmission are reduced as much as possible, the different parts of the algorithm are mapped appropriately using parallel pipelining methods. In addition, this paper proposes an image registration algorithm based on improved random sample consensus method which intends to get a higher calculation accuracy and a faster calculation speed.After pipeline dismantling and mapping image registration and processing algorithms, we test the parallel computing on reconfigurable processor simulation test platform based on So C Designer, and also test the serial computing of the corresponding algorithms on Atom 230 test platform. Experimental results show that computational efficiency of implementation of normalized cross-correlation, random sampling consensus, two-dimensional discrete cosine transform algorithm using parallel pipelining method is 28.24 times, 5.12 times and 8.29 times respectively of that of traditional serial implementation method. In addition, Simulation results show that the average of scaling error and rotation angle error of improved image registration algorithm are 0.18% and 4.34% respectively, of which the registration accuracy is higher than that of the standard RANSAC registration algorithm, of which average of scaling error and rotation angle error are 0.34% and 15.16% respectively. In the cases of different number of pairs of feature points and different ratios of the outliers, the computational speed of improved algorithm is 8.97 times to 163.79 times of the computational speed of standard algorithm.