Research On Coarse-grain Reconfigurable Architecture Base On Loop Pipelining

In recent years, coarse-grained reconfigurable architectures have become increasingly important alternatives for accelerating multimedia applications. More and more coarse-grained reconfigurable architectures have been proposed. Coarse-grained reconfigurable architectures become important due to its combination of the advantages of both ASICs and general processors. However, recent architectures have complex processing elements and network without utilizing the character of programs. The research of this paper trys to design a coarse-grained reconfigurable architecture with simple processing elements and network, which can put the architecture and computation together.In this paper, we propose a coarse-grained reconfigurable architecture named LEAP (Loop Engine on Array Processor), which is based on loop pipelining execution mode. The LEAP architecture is a data-driven architecture, which has a reconfigurable processing elements array and data memory that provides reconfiguration. This architecture aims to map the expression statements of high level programming languages onto processing elements and build a pipelining dataflow structure according to a static dataflow graph, and accomplishes tasks automatically and efficiently for applications.The LEAP architecture has many important features. It has a technique provides loop self-pipelining execution and a reconfiguration mechanism to maintain applications consistency while minimizing the impact on performance. To achieve loop self-pipelining, balancing is performed through addition of more storage (i.e., FIFOs) in each processing element. The bandwidth of local memory can be ultilized fully for best performance using memory scheduling, and the time for data transmitting is hided by the concurrency of data transfer and computation.To demonstrate the effectiveness and excellence of LEAP architecture, this paper provides some case studys of algorithm mapping to the LEAP architecture. At last, two prototyping phases of the LEAP architecture have been implemented on an Altera FPGA EP1S80F1508C6. The host computer can communicate with the LEAP prototypes through PCI bus, and testbench codes have run successfully on the prototypes.