Research And Implementation On Reconfigurable Hardware Architecture Of Speech Enhancement Algorithm For Bone-conduction

The application of bone-conduction technology has changed the traditionalconception of hearing. One of the advantages of bone-conduction is that people can hearvoice without ears but skull. However, the bone-conduction can not only transmit voicebut also transmit wind noise and grinding by the skull in actual applications, whichdisturb the efficiency of voice transmit. Using speech enhancement can effectivelyreduce the noise in bone-conduction application, improved the quality ofcommunication.This paper studies the speech and noise characteristics, analyzes the non-stationarynoises when communication with bone-conduction technology. Several speechenhancement algorithms is analyzed and compared. According to the characteristics ofthe bone conduction speech enhancement, using the speech enhancement method basedon the speech and noise’s dictionary learning. Then set up an experiment environmentfor the speech enhancement algorithm simulation and finish the simulation experiment.The simulation has obtained an ideal result. According to the computational features ofspeech enhancement algorithm, the speech enhancement system architecture is designed.The works mainly design and simulation the reconfigurable co-processor unit on RTLlevel mode. The design obtained a good simulation performance.This paper’s main research work and achievement include:1. On the analysis of the existing main speech enhancement algorithm anddictionary training algorithm based on practical, real-time and convergence, the speechenhancement method based on signal dictionary. This paper using K-SVD and OMPalgorithm to learn dictionary of signal for obtained speech and noise dictionary.2. Based on Matlab software platform, an experiment environment is setting up forthe speech enhancement algorithm simulation. Using the speech data collected withbone-conduction equipment for speech enhancement algorithm simulation. Theexperimental results show that the proposed method effectively reduce thenon-stationary noises when communicate with bone-conduction. After denoisingprocess, the enhanced of SNR ratio more than10db and the intelligibility of speech iswell.3. We propose a architecture with reconfigurable co-processor which canefficiently accomplish speech processing based on analysis of algorithm features andcomplexity. And implement the RTL level design. The design implemented withreconfigurable coarse-grained, VLIW compute mode and partial interconnection. Thearchitecture’s feature is coarse-grained parallel processing, multiple-context andself-loop pipelining which has good parallel performance with hardware acceleration forthe speech enhancement. 4. Mapping the arithmetic of FFT, matrix multiplication and vector dot productonto reconfigurable coprocessor is studied in this paper. And these arithmetic aresimulated on the reconfigurable hardware simulator which describe the RTL HDL. Thesimulated results show that reconfigurable processing element speed up intensivecomputing of speech de-noising algorithm. It can meet the application requirement ofreal-time speech denoising processing of bone-conduction.