The Research And Implementation Of Encoding And Decoding Algorithms Of Rate-Compatible LDPC Codes

Low-density Parity-check Codes(LDPC codes) is a linear block code based on sparse check matrix.It's Gallager who initially invented the LDPC codes.Several decades later,MacKay and Neal rediscovered it and proved that its performance was close to the Shannon limit when combined with the iterative decoding which based on the BP(Belief-Propagation) Algorithms. Research shows that when these codes are long enough,the performance of LDPC codes are more excellent than Turbo codes,and its complexity of decoding is less.By now,it has been adopted for error-correcting coding in the fourth-generation mobile communications system by a lot of company.More and more people are bound to research on it.In the time-varying fading channel,the strategy for error controlling is that the coding rate is based on the condition of the channel.The effective way to realize this strategy is to use the rate-compatible codes which are widely adapted in the HARQ system too.It was Li J.and Narayanan K who applied the concept of rate-compatible codes to the LDPC codes for the first time.The rate-compatible LDPC codes(RC-LDPC Codes) that they constructed has become one of the most popular issues studied by us.In this paper,the author gives us a systematic analysis and research about rate-compatible codes and LDPC codes.Meanwhile,the author carries out an in-depth study of the encoding and decoding algorithms and the construction about the rate-compatible LDPC codes.As a result,the author constructs a kind of rate-compatible codes and shows the fast encoding algorithm for the special structure.In addition,the author analyses the Normalized BP-based algorithm which is able to be implemented in the hardware platform.Through simulation,the author gets the normalized factorαwhich is suitable enough to make the performance of decoding algorithms close to the BP algorithms'.And the author also construes the data quantization for the hardware implementation.Finally,the author designs the encodesr with the FPGA platform according to the algorithm presented in this paper. The following tasks have been finished:1.In this paper,the structure of Repeat-Accumulate Codes(RA Codes) whose codes rate is 1/2 with length of the codes is 1152(expansion factor z=48) in the standard IEEE802.16e has been modified,without the loss of performance.The author constructs the parent codes which is linear-time encodable and suitable for expansion and delete in order.The structure of the parent codes in this article is called LTE-QC structure,namely,Linear-Time Encodable Quasi-Cyclic structure.And LDPC codes with this structure of the LTE-QC in this article are called rate-compatible LTE-QC-LDPC codes.2.In this paper,a rate-compatible LDPC codes whose codes rate is 6/10,6/11,6/12 and 6/13 is constructed,which is with LTE-QC structure,using the method of expansion and delete in order.The author also brings out fast encoding algorithm,in corresponding for its structure;In this paper,the rate-compatible LDPC Codes ensures that higher bit rate codes can be nested at a lower bit rate codes;each bit rate is corresponding to a fixed checking matrix.In practical application system,this can avoid transmission of the deletion matrix,reducing the overhead;the structure of encoder to achieve in hardware is simple and easy to implement,and also easy to implement on logic control.3.As the Min-Sum decoding algorithm has nothing to do with the channel characteristics and is easy to realize,but with great performance loss,so in this paper the author studies a modified Min-Sum decoding algorithm,it is to say Normalized BP-based algorithm.And with Monte Carlo simulation method,calculate the normalized factorαsuitable for each bit rate,so that its performance can be close to BP decoding algorithm;simulation results show that the value ofαhas great influence on the performance of Normalized BP-based algorithms,in the condition of selecting a wrongα,the results will be very poor;different the value ofαwith different rate,the value ofαcan be close to 1 with the condition of higher bit rate and higher SNR(Signal to Noise Ratio).The performance of the Min-Sum decoding algorithms is very close to the performance of BP algorithms',we can make no change to the Min-Sum decoding algorithms,usedα= 1 directly.4.Take into account that we needed to quantify the data during the hardware realization, analysis the quantitative median of intermediate variables in the process of signal receiving and decoding,the relationship between the quantitative median and decoding performance are given through the simulation;in this paper the author proves that when using 6bit uniform quantization for the received signal,8bit(the highest bit is the sign bit,the other 7 bits mean size) uniform quantization for the intermediate variables in the decoding process the BER(Bit Error Rate) performance has no loss compared with non-quantitative performance,in the case of a higher SNR even better than the non-quantitative performance;But using 5bit uniform quantization for the received signal and 7bit(the highest bit is the sign bit,the other 6 bits mean size) uniform quantization for the intermediate variables in the decoding process the BER performance is no much loss(＜0.1 dB) than the non-quantitative performance;So if the performance requirements are not so strictly,using 5bit uniform quantization for the received signal and 7bit uniform quantization for the intermediate variables in the decoding process is acceptable.5.Finally,in according to the rate-compatible codes and its rapid coding algorithms constructed in this paper,the rate-compatible LDPC codes encoder has been designed in the FPGA platform;the rate-compatible LDPC codes encoder designed in this paper has a completely parallel structure,without taking the speed limit of serial bit stream in the input and output modules into account,this encoder has a high encoding speed,the corresponding cost of the hardware resources are much,which is most applicable to the requirements of high-speed coding with the rich hardware resources;if the rate requirement is not very high,and the hardware resources are relatively short,a matrix multiplication unit which cost much resource can be changed into the serial or partly parallel structure to save resources.