Research On FPGA Implementation Of General High Speed LDPC Encoder And Its Application

The rapid development of high speed data transmission business makes a great demand on speed and quality in information transmission.Error correction codes can effectively improve the throughput in communication systems while keeping the constant power in the same level.In 1963,LDPC codes were proposed by Dr.Gallager.In the 1990 s,scholars rediscovered its advantages.As its upstanding performance,LDPC codes have been widely used in many communication standards.Designing high speed LDPC encoder and implementing it on FPGA is a very valuable job.In the time-varying channel,AMC & HARQ systems with rate compatible LDPC codes can improve the throughput effectively.This paper starts from a general encoding algorithm which deals with the consistent parity check matrix by the rank of replacement and Gaussian Elimination.Based on this algorithm,we propose an encoder architecture with simpler hardware implementation,shorter critical path delay and higher encoding speed in hardware design.In our scheme,the operation of the parity bit divides into multi-step with parallel computation.We show the implementation results on the FPGA chip,and optimize its structure to guarantee that it can be applied to the AMC & HARQ system.Achievements and the main points of this paper are brought forward as follows:1.Based on the existing encoding algorithms,this paper proposes an optimal encoding algorithm which deals with the consistent parity check matrix by the rank of replacement and Gaussian Elimination.As a result,the operating of each parity bit will only relate to the corresponding row of the preprocessed matrix,which guarantees a flexible parallel structure.The algorithm can be also applied to random constructed LDPC codes,which can improve the error correcting performance.2.This paper proposes an encoder architecture with simpler hardware implementation,shorter critical path delay and higher encoding speed in hardware design.In our scheme,the operation of the parity bit divides into multi-step with parallel computation.In order words,all parity bits will be computed simultaneously and each of them will be operated step-by-step.By the Vivado15.3 hardware development environment,the simulation,synthesis,placement and routing of the encoder has been carried on.To verify the correctness of the work,the board-level verifying also has been finished on Xilinx company Virter-7 series FPGA chip.The numerical results show that the working clock frequency of the encoder can reach 270 MHz with 15.1Gbit/s throughput.3.A kind of RC-LDPC codes with 7 rates is proposed,check matrix of lower rate codes nested in higher rate ones,which can be dealt with the encoding scheme based on Gaussian Elimination.To make it can work with this RC-LDPC codes,the structure of the above fixed rate LDPC encoder has been improved,by designing a rate selection module additionally.When working in an AMC & HARQ system,this LDPC encoder can improve the transmission of the communication system efficiency.Because of the simple structure of the control module and outputting module,the compatible rates encoder doesn't consume much more hardware resources compared with the fixed rate one.