Design And Implementation Of DAQ System Based On Tiadc

With the development of wireless communication technology, the frequency and bandwidth of signals got by digital receiver is increasing, it is obvious that the speed of data acquisition, transmission and storage has higher and higher requirement. Although the analog-to-digital conversion (ADC), devoted to have high speed, it is limited to the production process, resulting in a bottleneck of rate of a single ADC. Multi-channel time-interleaved ADC sampling technology arises at this time. However, the existence of channel mismatch errors have greatly influence on the system, it is quite significant to research the calibration method both at home and abroad.In this thesis, research is starting from the channel mismatch errors, focusing on the clock interval mismatch, and adopting the method of digital domain blind estimation to calibrate it. Focusing on the influence to the performance of system brought by clock interval mismatch, it is important to research the digital domain blind estimation and calibration method of clock interval mismatch error, using statistical analysis method to estimate error, adopting the error accumulation method to optimize the calibration process. Summarizing the work, Firstly, a time-interleaved ADC structure model including clock interval mismatch error is adapted, it is used to find out the source of clock interval and analyze the influence on system. Then, sampling a single frequency sine signal conforming to Nyquist, using statistical analysis method to calculate the difference expectations of numerical code acquired from sine signal between adjacent sub-channel, acquiring the estimated number of time interval. Lastly, considering a Negative impact of clock jitter produced by real-time feedback of clock interval mismatch error, it is necessary to optimize the calculation method by accumulation of interval mismatch error.In this thesis, two pieces of ADI company chip, AD9648, combining Altera's FPGA chip, Cyclone IV EP4CE115, are used to set up a 200MSPS,14bit dual channel time-interleaved system, which is used to verify the digital domain mismatch error calibration method. The experimental results show that the system can collect the input signal bandwidth of 80 MHz, in addition, in the application of digital domain calculation method of clock interval mismatch error based on FPGA, the SNR arrives 68 dB, which has an upgrade of 19 dB.