Analytical Modeling And Validation For Access Performance Of DDR Memory System

With the development of process technology, the requirements of SoC memory latency and bandwidth are upgrading. As a result, memory system has become an ever-tightening bottleneck for SoC performance. When faced with the complex design of memory system, the traditional simulation models with slow speed has been unable to meet the demand. To improve the abstractive level, system-level design becomes the necessity to solve problems. Using mathematical methods to build analytical model for memory system can quantitative analyze the influence factors, greatly reduce the performance evaluation and verification time. The analytical model has the characteristics of high flexibility and fast simulation speed.This thesis focuses on high-level performance evaluation for DDR memory systems and studies the DDR memory access latency and bandwidth, then, builds an analytical model to evaluate the performance. Existing analytical modles of memory access latency can not analyze the access process comprehensively, resulting in large access latency errors. In the thesis, the access latency is divided into two parts, one is the DDR delay timing constraint, and another part is the latency of DDR memory controller. Memory access latency is established based on M/D/1 queuing theory model and memory access pattern. For modeling memory access bandwidth, timing parameters are collected by analyzing memory access trace to calculate the DDR efficiency and evaluate the memory bandwidth. Finally, the performance parameters from the analytical model are compared with the simulation results based on the DRAMSim2 to evaluate the applicability and accuracy of the analytical model. Results of the experiment show that, compared with the simulation model results, the error of memory access latency is less than 10% and bandwidth error is less than 20%. Meanwhile, the evaluation time is decreased by 81% to save the verification time.The analytical model for DDR memory system can evaluate the system performance effectively. Compared with the simulation model, the analytical model can get the evaluation results of DDR memory system performance in a faster time to achieve efficient SoC design.