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Modeling Memoey-level Parallelism Of Cache Analytically

Posted on:2019-04-08Degree:MasterType:Thesis
Country:ChinaCandidate:Q WangFull Text:PDF
GTID:2428330590475482Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Cache miss has a huge impact on the processor performance.Non-blocking Caches can handle multiple outstanding memory requests simultaneously to reduce the overall latency that processor waits for memory requests.Memory-level parallelism,as a significant metric for evaluating non-blocking Cache performance,refers to the number of Cache misses processed concurrently.It is difficult to evaluate memory-level parallelism by simulation or analytical model.By quantifying the effect of Cache miss rate,an analytical model of memory-level parallelism is proposed,which performs more accurately than existing works.The work of this thesis mainly includes two aspects.Firstly,given the previous analytical models of memorylevel parallelism based on the dependent relationship between memory references,this thesis analyzes and summarizes the relationship between factors and memory-level parallelism.These factors including the number of memory instructions,the number of memory instructions on the critical path of the memory references,the size of reorder buffer and MSHR.Moreover,the work of models is reproduced in the gem5 simulator to obtain the accuracy of models.Secondly,an analytical model of memory-level parallelism is proposed by analyzing and verifying the impact of Cache miss rate.Under different combinations of Cache size and reorder buffer size,the model's input is researched in depth—the miss rate in the instruction window to reduce the sampled number of model inputs.At the same time,the implementation method of this model is introduced in detail.15 benchmarks,chosen from Mobybench 2.0,Mibench 1.0 and MediaBench II,are adopted for evaluating the accuracy of our model.Compared to gem5 full-system simulation results,the largest root mean square error for multiple architecture configurations is less than 11%,while the average one is around 7%.Compared to the models proposed by previous researchers,the accuracy is increased to 15%.Meanwhile,the memory-level parallelism forecasting cost can be sped up about 38 times compared to the gem5 full system simulations.
Keywords/Search Tags:Non-blocking Cache Performance Evaluation, Memory-level Parallelism Modeling, Cache Miss Rate, Memory Dependencies, Analytical Model
PDF Full Text Request
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