An Analytical Performance Model For Networks-On-Chip In MP-SOC

With the rapid development of mobile devices,SOC designers start to intergrate different processing elements (CPU,GPU,VPU,DMA,etc)in SOCs,forming Heterogeneous MP-SOC to meet the need in multimedia applications.it’s been proved to be more efficient for designers to choose Network on Chip to optimize the interconnection performance in Heterogeneous MP-SOC.In the process of designing and optimizing NOC, analytical models appears to be more effeicient compared to systematic simulation,and is a better way to evaluate the interconnect performance.In terms of different scenarios,the workload of interconnect need to be analyzed according to application, mapping and allocation strategy,etc.based on the QT,we considered the burstness of the masters in typical scenario,by using a mmpp(2) process as an injection process,we created a new mmpp(2)/M/1 queue model to improve the conventional latency model.In order to show the new model is more capable of approaching the real stats obtained from the simluations, we used a software platform in the evaluation phase of the establishement of an analytical model of NOC.In order to make it suitable for our search,master device communication senarios are analysed based on the task allocation, and the parameters like wire delay are adjusted.In the experiments, it’s proved that the accuracy of the new model compared to simulation is at least 15% better than the formal one.The work showed that with the specific modeling and optimizing, the accuracy of analytical model of NOC can be further upgraded. Compared to simulation, NOC analytical model can give out accurate result in shorter time,thus is able to fasten the flow of software-hardware co-design.