Research Into High-level Performance Estimation For SoC Of Mobile Intelligent Terminals

With the increasing complexity and tight time-to-market schedules, SoC design is faced with tough challenges, and high-level performance estimation is the key to the effective design. Accurate pre-silicon estimation of performance can help designers make decisions which meet the requirement in the early design stage.This thesis focuses on the two key phases of application-oriented performance estimation in the pre-silicon design phase.1) Workload:massive amounts of applications are regarded as an original set, and a method for extracting the representative subset is proposed, which is used to construct the benchmark suit for the general-purpose application; 2) Hardware model:for the minimum system composed of the micro-processor and the DRAM memory system, a method based on the analytical model for performance estimation is proposed. The main achievements and contributions are as follows.1. A method based on the genetic algorithm for benchmark subsetting is presented. This method can be used to extract the most representative subset (representativeness is quantified by the mean error of CPI) from the original set of benchmarks for the general-purpose application. It is not easy to be trapped into local optimization and is insensitive to noise, overmatching other known methods. Compared with the common used method based on k-means clustering algorithm, the subset extracted using the method presented in this thesis is more representative, with the mean error of CPI reduced by about 16%.2. A relationship model between program execution time and memory access latency based on the independency of instructions is presented. The effect of memory system on the execution time should be considered to estimate performance accurately. In the traditional linear regression model, the execution time is linearly correlated with the access latency, having a major error. In this thesis, the mechanism of the nonlinear correlation is shown, that is some instructions are independent, performed in parallel with the memory access and the parallelism is related to the access latency. The model presented can be used to predict the practical execution time with a given latency, and the average prediction error is 2.03%, lower than the error of the linear regression model, which is 14.43%.3. An analytical model of memory system based on the service window of requests is presented. Memory access latency is the critical performance metric, and is hard to be estimated because it is dynamic and influenced by many factors. The traditional model is based on the queuing theory with an assumption that the inter-arrival times of requests are specifically distributed, making the application scope limited. In the experiment of this thesis, the maximum prediction error of the access latency is 34.82%. In this thesis, it has been found that the queuing delay of requests in the DRAM memory system is linearly related to the memory busy time. Taking all factors into account, the presented model based on the service window of requests must not rely on the assumption of the inter-arrival time distribution, and can be used to predict the access latency of memory systems in different configurations with the error lower than 11.93%.In conclusion, the method based on analytical models for performance estimation is presented in this thesis, including extracting representative benchmarks for the general-purpose application and high-level hardware modeling, which can be used to predict the application-oriented performance of SoC in the early design stage. This method is applied in the development of an SoC for one of the National Science and Technology Major Projects on Core Electronic Devices, High-end Generic Chips and Basic Software, providing an effective decision support for designers.