Research On Analytical Modeling Of Memory Subsystem Performance

Using models to quantify the relationship between memory patterns and memory techniques should be a necessary step to design a high performance memory subsystem.This dissertation proposes the miss predicition models and the miss penalty models for multi-level caches and the DDR controller,which constitute the memory subsystem.By combining all the models of different hardware components,the performance of various memory subsystems can be evaluated accurately and fast.In the view of the memory hierarchy,the contributions of this dissertation can be classified as follows: For modeling the L1 Cache misses,this dissertation constructs an empirical model based on the stack distance variation coefficient.The classical method ignores the impacts of out-of-order techniques on memory behaviors,which makes the prediction error as high as 17%.This dissertation uses formulas to describe the relationship between the out-of-order references and the stack distance changes.By means of machine learning,the undetermined coefficients that cannot be theoretically derived are automatically solved,in which the prediction accuracy is increased from 83% to 95%.Because it is impossible to obtain the memory references to the downstream caches without any simulations,the classical models can merely predict L1 Cache misses.This dissertation proposes a mechanism model based on full-probability events for modeling the L2 Cache or lower level cache misses,which combines the arriving probability of downstream requests with the conditional probability of upstream cache misses.By traversing all scenarios,the downstream cache miss rate can be calculated using the full probability formula.Experimental results show that the proposed model can accurately predict the downstream cache misses with an accuracy of over 94%,which greatly expands the usage of the classical models.Meanwhile,this dissertation optimizes the memory level parallelism(MLP)model,while taking the impacts of multiple data dependences in the instruction windowa and cache miss rates into considerations.The MLP prediction accuracy has been increased from 72% to 96%.In addition,for the MSHR with multiple target slots,this dissertation supplements the the calculation of effective service time for cache misses,which improves the penalty prediction accuracy by 20%.Furthermore,this dissertation deduces a DDR latency model,while the input is the memory stride distribution.Recent researches assume that the arrival rate of memory requests satisfies the Poisson distribution,which is not satisfied in singlecore architectures,while the prediction errors of such models are more than 20%.This dissertation constructs the DDR latency model by deriving the relationship between the memory stride distribution and the hit rate of DDR row buffer.Compared with previous studies,the prediction accuracy could be increased by 14% in single-core processors,while the errors in multi-core processors remain the same as previous studies.By combining the analytical models of each hardware module,this dissertation gives performance predictions of the memory subsystems for Loongson GS264 and ARM Cortex-A9.Under 49 benchmarks,the prediction accuracy is 93%.In addition,this dissertation utilizes analytical models to study the memory performance differences and help to locate the performance bottleneck of Loongson GS264 memory subsystem,after which this dissertation provides the optimization suggestions.