Power And Timing Optimization Based On National Security Chips

With the development of integrated circuits,the performance of processor is getting stronger and stronger,the storage capacity of mobile devices is getting larger and larger,and the Internet is accessed more and more frequently.Our daily life is inseparable from mobile devices,but mobile devices are too slow to operate,within a powerful data protection system,where data can be easily stolen and face greater risk.S ecurity problems can even bring huge risks to national defense.Usually,security problem is mainly solved by software encryption and decryption.However,software defenses can't cope with a large variety of attacks.And large amounts of data require a lot of processor resources and energy consumption for software.This article provides a security chip based on the National Security algorithm of China,using hardware technology to encrypt and decrypt data,which can be widely used in mobile devices,mobile payment,smart home and other fields.Based on the ARM core,the chip adopts the key technologies of SOC design and integrates high and low speed interfaces of various storage media.It combines the national security encryption and decryption technology,and has the advantages of fast operation and low power consumption.The security chip is mainly used for mobile devices,which posed a challenge to the back-end design.Mobile devices put new demands on the chip's speed and power consumption.Whether timing can meet requirement directly impact on the chip speed.Timing analysis and violation process propose new problems of the design.After the chip placement and routing,netlist and interconnect delay files(.SPEF)are extracted,and the static timing analysis of MCMM(Multi-corner Multi-mode)is performed by using the timing analysis tool—Primetime(STA,Static Timing Analysis),and fix it with ECO(Engineering Change Order)against the timing violation in the timing analysis result.With ECO commands,the workload for modifying the timing can be greatly reduced.For the technical problems of low-power security chip,this paper provides a method and process of back-end design and timing analysis,which is the core work of this paper.At the same time,this article introduces the source?principles and analysis methods of in the backend design,and methods used to reduce power consumption,and gives the results of optimizing power consumption.After tape out,the chip successfully run.The operating frequency is 36Mhz;working temperature is 0 °C to 80 °C;typical operating current is 5m A;SM2 encryption speed is 18 Kbps,decryption speed is 23Kbps;SM2 signature 71 times/s,verification speed 37 times/s;SM3 Hash value generation speed is 17.5Mbps,SM4 encryption and decryption speed is 12.36 Mbps.We can see from the data above that the chip performance meet industry standard,which supports true random number generator and physical unclonable function module(PUF),with very good performance.