The Study Of RISC_CPU Backend Design Based On Encounter

With the progress of science and technology and the demand of people constantly improve, more and more high-tech products in succession, and these products appear mostly benefit from the development of integrated circuit technology. According to Moore’s law, integrated circuit of the integration will double every 18 months, and make the process size declining. Declining process size can make the parasitic effect becomes more severe, timing convergence difficulty increases. Considering the parasitic effects caused by signal integrity, dynamic voltage drop and high integration, above GHz frequency, timing convergence problem is difficult to be resolved just by the improvement of technology. As a physical implement designer, the task is how to reduce the cycle of chip design and how to make it fast into the market. Therefore, the physical design is not just familiar with the whole flow of backend and familiar with EDA tools but needs to have good thorough understanding for the overall characteristics of the target and physical implementation method. In this paper, it completes the physical design of the 8 bit RISC_CPU based on TSMC 0.18 um 1P6M CMOS process. The author’s major contributions are outlined as follows:1. Logic synthesis has been studied. Logic synthesis is a process of synthesizing and mapping a certain function of the RTL code into circuit structure, this paper mainly studied how to add timing constraints and to set work environment for the target design in the process of logic synthesis, at the same time, this paper expounds the handling method of timing constraint for multiple clock domains and implement process of logic synthesis and the optimization method for the path in violation. Based on the above theory, the 8-bit RISC_CPU timing constraints are added, working environment is setted, implements the design of logic synthesis, after synthesis checking the timing report to make sure the sequence converge, optimize the design goal of logic synthesis to generate gate-level netlist. Finally logic equivalence check by Formality is made between netlist and RTL code to verify the consistence of logic function. Making sure the logic functions descriped by the netlist file after logic synthesis and the RTL code are consistent2. Design for test has been studied. Along with the development of the scale of integrated circuits, testing costs accounted for more prominent, in order to reduce the cost of testing cost in the design process, reduce the probability of failure, improve the quality of design and production yield, measurability design is widely used in the chip design. The basic theory and common testing methods and common fault types of measurability design are introduced in this paper and discusses the design of test rules, completes the 8-bit RISC_CPU scan test and fault test, finally it carries on the test coverage of the examination, improves coverage and inserts the scan chain in the design.3. Static timing analysis has been studied. This paper discusses the basic principle of static timing analysis, delay calculation and parameter extraction method. The sequential path dividing and timing analysis and checking violation path. Introduces the common timing violation factors and the sequence optimization method. timing analysis method under the condition of OCV and common path pessimistic path is mainly introduced, this paper adopts CPPR(CRPR) method to complete the 8-bit RISC_CPU timing analysis, ensure that timing sequence meets the requirements of timing constraints.4. Physical design has been studied. This paper expounds the design of digital back-end design flow, the content of the floorplan and the impact on subsequent design of its result is studied. In the phase of the clock tree synthesis, adopted the combination of manual and automatic methods for the design of the clock tree synthesis, minimize clock skew between the leaf nodes. Finally, the netlist after the routing and before are by formal verification completed consistency check, validating the correctness of the physical implementation process.