Design And Implementation Of Bit Error Test System Based On VSC8248

In the information society, communication has been become indispensable part of life. The demand of information to the people become more and more large, the traditional electrical signals as the carrier of the communication system, transmission system will gradually be instead by light for carrier transmission system and communication system. Optical communication system transmitted large capacity of the information, rapid transmission speed, strong anti-interference ability, this makes communication system reliability and validity are has been greatly improved. Therefore, optical communication system is the most potential, is the development trend of the communication system Validity and reliability is measured communication system quality. In optical communication, data after sending equipment, transmission channel, receiving equipment inevitably will appear error, which affect the reliability of the communication system. Usually will appear in the process of communication bit error to measure the reliability of communication system is good or bad, so how to statistic a practical communication system bit error become the key performance to detect system is good or bad. High speed bit error test is used to test the bit error rate of optical communication system, it provides the best technology test plan for verifying the reliability of the system and diagnosing communication fault.This article in view of the current error test system can not meet the higher rate of optical communication system error test, developed a kind of test rate higher error test system. It’s very good compatible testing rate before high-speed bit error of the testing system, at the same time it will be continuous bit error rate test increased to11.318Gbps, mainly test bit error for the optical communication of the rate of different SFP, SFP+, XFP optical transceiver module error and verify the reliability. In recent years,10Gbps rate of optical system has been to build and put into use, developed the error test system that test rate as high as10Gbps is of great significance. This topic research of the high speed bit error test system is based on special bit error test chip VSC8248, test rate from1.0625Gbps to11.318Gbps, can be compatible with Ethernet, Fibre Channel, OTN, SDH, Infiniband test rate.The main work accomplished in this paper are as follows:The theoretical analysis the realization method, principle of work of the bit error test system, and puts forward a kind of error test design scheme of the system of test rate from1.0625Gbps to11.318Gbps, and through comparison of several schemes to choose the optimum design scheme., accomplishes the main points and ideas of the hardware design and software designDesign the hardware circuit of the high speed error test system based on VSC8248. Using high-speed circuit design theory knowledge to verify the feasibility of the circuit design, power supply system design in a switch power supply, and the combination of linear regulators power supply way, make whole power supply meet the requirements of low noise, high transient response, clock circuit can be designed to be programmed to change the output clock of the active clock frequency to meet all kinds of test rate required frequency.Achieving the main points and ideas of software design, considering the error test system of practical and ease, the system adopts the man-machine interface operation and single independent operation to realize the bit error test of the system; at the same time PC communications with serial communication and USB two communication mode, meet different interface of error test function.This topic research system test rate can amount to11.318Gbps, circuit design and the PCB design make use of high-speed circuit design and transmission line theory. This article from the signal integrity, integrity problem of power supply appeared in the circuit, theory analyze the high speed of the PCB design laminated design, termination design, impedance control design, EMC design, combined with the signal integrity simulation and power supply integrity simulation, provide the best solution for system PCB design, improve the system performance.According to the error test system low jitter requirements, theory analyzed the source of the jitter, through the choice of low jitter clock generator and clock buffers to design the low jitter clock generator circuit, combined with the design of high-speed PCB reduce the jitter caused by various noise, optimize the system jitter to meet the jitter requirements of the Ethernet Fibre Channel, and OTN, SDH, Infiniband network. Finally, this paper completed a error test system design, and through the physical testing to verify its performance. Completely covered1.0625Gbps to11.318Gbps speed rate of error test; the rise time of transmitter signal between in24ps-47ps, the peak-peak jitter is less than0.28UI, meet10G Ethernet, SDH standard; reciever sensitivity is35mv,the reciever sensitivity of the light of the XFP bewllow to-17DBM, fully satisfy the current measured equipment to the performance requirements of bit error rate test system.