A Study Of 8 Bit 20KSPS 0.4V Ultra-Low Power SAR ADC

Successive approximation register analog to digital converter(SAR ADC) is a kind of medium-sampling rate and medium-high-resolution conversion accuracy ADC, which has advantages of simple structure, small area, low cost and low power consumption etc, so it is relatively widely used in wireless sensor networking, portable equipment, medical electronics, precision instruments and so on. With the advance of the technology, the further decrease of the CMOS process size make the digital circuit achieved rapid development. To the ADC, especially SAR ADC, process improvement has brought a big leap in development for it has little analog block. In recent years, SAR ADC with its unique performance advantages has become a popular spot and has been widely studied by research groups. A series of chips with excellent performance has come out.An 8-bit 20 KSPS 0.4V ultra-low power successive approximation ADC is designed in this paper. With the study of various types of Charge redistribution architecture, we proposed a new energy efficient switching scheme. The way of taking the capacitors as a whole, greatly reduced the energy that the capacitor array consumed. Through the analysis of MATLAB model about some switch scheme, the energy consumption and area of the capacitor array have been optimized 99.9% and 75%, compared with the conventional switching scheme respectively. Since the energy consumption of the capacitor array accounts for the largest proportion of the whole system, it can be very effective in reducing the energy by using the new switching scheme. Because the power supply voltage is relatively low, the use of one stage bootstrap circuit cannot make the MOS transistor fully turned on and introduces a great deal of nonlinearity, so we use the two stage bootstrap structure. The leakage of the charge is serious in the situation of low power and low speed. We use the renewable latch mode in the logical block to reduce the leakage influence. In layout, an isolation between analog block and digital block is used and guarding ring around the analog block is added to improve immunity. To suppressing latch-up, double-well process was used in some MOS. Centrosymmetric structure is used in every block and foil capacitances were added around the capacitor array to improve the match of the capacitor array. In order to decrease the influence of mismatch, two dummy MOS were used around the input of the comparator.Based on SMIC0.18?m CMOS technology,we carried on the simulation after the layout has done. The core area is 1070×1240 ?m2. At 0.4V supply voltage and 20 KSPS sample rate, the SAR ADC achieves ENOB of 7.98 bit, SNDR of 49.799 d B, SFDR of 73.83 d B, THD of 69.55 d B, and consumes 19.76 n W. The FOM of the SAR ADC is 3.86 f J/conversion-step.