Study And Verification Of Shareable Cache In Multicore Processor Based On VMM

With the continuous development of the China's industrial sector and the advent of the digital information age,many domestic enterprise have been engaged in research and development of China-made CPU.New products based on ARM?X86?POWER and MIPS micro-architecture gradually enter the market.These processors we have contacted are von Neumann architecture, the most import feature of the architecture is access to the data..Cache is made of SRAM,it has a high read-write speed and a small area.Generally the Cache located between the centeral processor and main Memory,as a bridge to solve the speed problems between the two units.The main contents of the paper are functional study and Verification scheme design for a Last level Cache of a multi-core processor.The DUT located between L1 Cache and the Memory to manage the data transaction between them.This processor chip has 4 cores and16 threads.As the last level cache of the multicore processor,the DUT not only solve the basic function but also need to manage the coherence of Shareable-Cache.The chip use Lock-Grab scheme to manage the access of the shareable area,as the whole architecture designed based on ARM V8.The author study the main function module and design a complete Verification scheme. In order to guide the next work of verification, the Features and Tests Point are extracted and the author builds the functional coverage model according to the design specification of chip.At the end of the simulation,the autor combinates function coverage and code coverage to measure the quality of verification and finally finished the verification work.VMM(Verification Methodology Manual) verification methodology is the mainstream verification methodology in the industry today.The verification platform is built with System Verilog and based on VMM(Verification Methodology Manual).The author develop the Test Cases and do function simulation by using the Snopsys' s VCS simulator.In order to complete the verification work,the author use Code Coverage and Functional Coverage to measure the progress of the work.Coverage Driven Verifi Cation, Directed Test and Constrainted Random Verification are used at the same time during the simulation. The results are given by analysising the Code Coverage and Functional Coverage report, and also given the bugs which have been found during the simulation.Finally, the autor studyed the reusability of the platform into another verification platform named NOC,which has the same interfaces with LLC,and then it proved the platform has a good reusability.