Research And Implementation Of High-speed Image Processing Algorithm

As the wide application of digital camera with high resolution and frame rate, the high speed image processing technology is becoming increasingly important. This paper focuses on the research about high speed image processing algorithm and its hardware realization.This paper researches the image binarization, median filtering, edg e extraction and image scaling and so on, where the highest transmission rate of Camera Link interface can reach 850MB/s, resolution ratio is 2352*1728 and frame rate is 60 fps. Firstly, through it discusses the concept, performance and FPGA implementation method about the parallel pipelining algorithm. Secondly, after doing simulation with MATLAB and considering project difficulty, anti-noise performance and hardware cost, the paper chooses Sobel algorithm to implement image edge extraction. Thirdly, based on parallel pipelining structure, it carries out deployment process to the image processing. For the deployment process, the paper does co-simulation with System Generator to verify the correctness of the design. Finally, it realizes the high speed image p rocessing on hardware platform with Verilog HDL.In this paper, the traditional image processing algorithms and parallel pipelining algorithms are combined. When Camera Link interface works in Medium mode, except the high-speed I/O and Camera Link interfac es, all of the procedures are driven by 80 MHz. It's sufficient to handle the high-speed image data from Camera Link interface and the resource consumption of FPGA is less 60%. More-roads parallel deployment is reasonable and has more performance if the logical resources and memory bandwidth is enough. The design method of this paper is also applies to high speed interface like Coa XPress.