High-speed Image Number Of Recognition System Research And Implementation Based On FPGA

Image processing technology originated in the1920s. The late1960s to themid-1970s, with the associated technology in the scale, speed and cost of theimprovements, especially the generation of discrete mathematics and improvement ofthe digital image processing technology has been rapid development. Studied in thispaper digital image processing system, is divided into two parts, first part of the digitalimage acquisition, the main study to CIS+CPLD design to achieve high-speed imagecapture image; followed by digital image processing section, the main core of theFPGA, integrated pipelined parallel processing hardware module, complete the tediousrepetition of high-speed digital image processing. High cost, miniaturized design ofreal-time digital image processing to solve other computer systems in digital imageprocessing "congenital" insufficient bandwidth, computational efficiency is low andthe high cost and other issues.In this paper, CIS+CPLD design to achieve high-speed image data acquisition.The use of programmable logic device CPLD complete CIS image sensor driver andAD sampling timing control. By precisely controlling the operating frequency and theCIS acquisition time difference between the lines, to achieve the synchronousoperation of the sensor and the cash registers; and by controlling the AD acquisitionwindow to obtain images of the smaller effective address stored in the PC duringdebugging problems slow. In the course of the study, first conducted a hardware circuitdesign, circuit board and system debug. The second step to complete the various partsof the CPLD programming, simulation, and download experiments. The third step is tocomplete the commissioning work PCI1714acquisition card, including the preparationof image acquisition and image coding stored procedures, and finally complete theon-line debugging. In this paper, the image processing system for the FPGA core, withmedian filtering of image noise reduction, image done using Sobel operator edgedetection. Focus on FPGA-based digital image matching matrix constructed using theFPGA logic computing power to build digital image recognition matrix, to match thealgorithm based on image recognition to achieve synchronization.Finally, some have carried out various experiments, simulations and onlinedebugging. Image acquisition system, FPGA-based systems and image pre-processingand image recognition systems can achieve high-speed synchronous operation of cashregisters, good to meet the real-time requirements to achieve the intended purpose. Because the design uses a pipeline technology, highly efficient process for theapplication of image processing systems and provides a new technology researchprogram.