| RF low noise amplifier is mainly used for weak signal received by the antenna to amplify and improve the signal to noise ratio. As the first block of RF receiver, the performance of the receiver is hugely affected by its noise figure, gain, linearity.As CMOS technology feature size is reduced, high frequency characteristics of CMOS devices are also rising. Comparing with traditional RF process(like GaAs, BJT), CMOS technology becomes more competitive. Furthermore, with the features of low-power level and high integration, CMOS technology is the future trends.Nowadays, the wireless network technology is widely used and the limited channel public resources of ISM 2.4G band have been depleted. In order to solve the problem of channel congestion, IEEE organizations continue to launch new wireless communication standards. Among them, the introduction of 5G wireless communication standard is an effective way to solve our current problems.This LNA is based on CMOS technology working at 5G band. Using 180 nm Chrt18_rf processes. A comprehensive study of the process is carried out, and their equivalent circuit model and mechanism of noise is fully studied. Then we have introduced a new graphic design method which is more accurate and efficient than the traditional calculation method to complete the LNA design. This method can also be implemented while both minimum noise and a maximum power gain are achieved. In order to design a high-performance low-noise amplifier, we also adopted an additional on-chip inductor technology library, hugely improved the accuracy and flexibility of integrated on-chip inductor design.The performance of this CMOS 5.25 GHz LNA design is that the Gain is 15.2dB, noise figure is less than 2dB, S11 is less than-15 dB, power consumption is less than 10 mW at 1.8V voltage supply. 1d B compression point is-18 dBm, IIP3 equal to-5dBm. Good result are achieved which also confirmed the feasibility and reliability of this design method presented in this paper. |
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