| With the progress of CMOS technology, the accumulation-mode MOS varactor (AMOSV) has been introduced into radio frequency integrate circuit (RFIC) regime for over twelve years and the models and fabrications in CMOS standard process of AMOSV have been well developed. Also, with the development of silicon-based technologies, the Moors' law is challenged ever. The increasing cost and scaling difficulties of CMOS transistors may give different technology or analog circuit techniques an opportunity. In frequency conversion RFIC design world, instead of the traditional resistive-based techniques, such as MOS transistor-based, diode-based and so on mixing techniques, a reactance-based i.e. AMOSV-based parametric design have no DC power consumption, high speed response, low cost, and low noise advantages over resistive-based design. Thus, it may have an opportunity for the reactance-based mixing technique in RFIC.;In this thesis, a 22-to-9 GHz AMOSV-based single-ended downconverter has been introduced with measured maximum 25.85-dB conversion gain in lower sideband downconverter configuration and n.8-dB conversion gain in upper sideband downconverter configuration. A 0.5-to-35.5-GHz AMOSV-based single-ended upconverter has achieved maximum 13.96-dB conversion gain in upper sideband configuration and maximum 13.12-dB conversion gain in lower sideband configuration. In the upconverter design, it utilizes the on-chip floating shield slow-wave mode coplanar waveguide (S-CPW) filters to save the chip area. An AMOSV-based single-ended frequency doubler is designed to accomplish an output between 94 and 108 GHz with minimum measured 14.5-dB conversion loss with on-chip floating shield S-CPW implementation. |
