The Design Of Gigabit Bit Error Tester Based On FPGA

With the development of communication technology, communication speed has increased. Communication methods and communication media are also changing, traditional electrical signal communication is gradually converted into optical signal communication, so most of the transmission is in fiber, BER tester is indispensable equipment in performance testing and fault diagnosis of the communication equipment and communication systems. The traditional low-rate signals BER tester with low bit error rate, single interface, and does not have optical interfaces; can not meet today's optical fiber communication system bit error testing. This paper focus optical fiber communication systems SDH/SONET (synchronous digital network) characteristics, designed the BER tester whose maximum speed up to 2488.320Mbps, the tester can detect the error performance of electrical communications equipment, but also can detect the error rate performance of optical communications equipment.This thesis analyzes the BER tester requirements, proposed XILINX's FPGA (model XC5VLX50T-1FFG1136) as the core hardware, and software as the management platform of BER tester. FPGA as the core hardware can overcome the shortage of traditional BER tester, for instance, digital signal processing, system expansion and real-time process, error detection soft-core can be designed using the hardware programmability of FPGA (field programmable gate array), so that the function of each functional module can be changed in the logic gate level, it was very convenient to manage and organize test data based on the use of personal computer.This thesis analyzes the principle and the m sequence error detection method, detailed description of the serial and parallel m sequence generation algorithm, designed low-speed error detection IP core and high-speed error detection IP core with the Verilog HDL language and then integrated the error detector system on the FPGA, improves system integration, the BER tester on a chip can output up to 9 error detection test code, can be applied to a variety of BER test. This BER tester auxiliary management software can select the test pattern, pattern rate and the test interface flexibly, also able to record continuous error happen time and calculated bit error rate automatically.According to the results of the design, The BER tester Based on FPGA core, supplemented by host computer interface software increase the system integration, expansion the function of the testing, After 8 consecutive hours of error performance test, the test results is accuracy, so The BER tester fit for the error performance testing requirements of today's SDH network equipment whose peed up to 2488.320Mbps, and achieve the expected goals.