The Design Of Bit Error Rate Tester Based On FPGA

With the development of serial transmission mode, data transmission rate hasalso been significantly improved, while the communication system needs to get thehigher transmission reliability, the bit error rate is a very important indicator toevaluate the reliability of the communication system. Bit error rate tester is a basictest tool to test the reliability of the communication system. The existing domestic biterror rate testers have the lower rate, and do not have the optical interfaces and thefunction of protocol test, foreign testers have better performance and higher test ratethan these in the domestic, but they are very expensive. For this case, it is necessaryto design a high-speed bit error rate tester with simple operation.This paper analyzes the advantages and disadvantages of the existing bit errorrate testers, and uses an internal integrated high-speed transceivers FPGA (model5SGXEA7K2F40) as the core hardware, ARM7controls peripheral keyboard displayand serial communications. This design makes full use of the advantages of FPGA insignal processing to make the test rate up to12.5Gb/s. This paper analyzes testprinciple and method of m-sequence by using the programmability of FPGA, anddesigns serial m-sequence and parallel m-sequence generation circuits, and thesystem can output six different length of test codes. This paper designs the externalinterface circuits, serial communication and data conversion circuits of the bit errorrate tester. Quad Small Form Factor Pluggable (QSFP) optical module interface cangrt high-speed optical signal transmission. This design can generate jitter signal andoutput trigger signal. The jitter signal can be used to test serial transmit protocol’sjitter tolerance testing, trigger function provided trigger signal to external devices,and the design has a PCI-Express interface, data can be transmitted by this interface.Bit error rate tester in this paper makes test rate improved greatly, and makes thetest code easily produce and statistics, the function of generating the jitter signalallows the design to be used to test the protocol jitter tolerance, the application fields of the design greatly is expanded. Every module of the system is simulated byQUARTUS II software to prove the reasonableness of the design.