Image Perspective Transformation ASIC Design And Verification

Image perspective transformation mostly be applied in image processing systems for image recognition and automatic target recognition, which is widely needed in various circumstances and situations. Currently this algorithm is used in hot fields such as navigation system, virtual reality system, road marking lines recognition, licence plate recognition, bar code recognition, and so on. Therefore the real-time demand is high.As one kind of image geometric transformations, perspective transformation, the most complex kind, contains rotation, zoom, and shearing operation. The features of this algorithm are complex calculation, multiple parameter, multiple steps, and changing mapping relationship for the image pixel. Thus, Currently the perspective transformation usually implemented by software or FPGA hardware.ASIC, short for Application Specific Integrated Circuit, is a kind of circuit that specially design for a specific algorithm or application. Comparing with general chip like embedded CPU, DSP and FPGA, ASIC has advantages in calculation speed and producing cost for specific algorithm.Based on detailed analysis the algorithm, this paper propose a hardware architecture to implement the algorithm. Other works include algorithm simulation, RTL coding using verilog HDL, and function simulation and verification. Specially, for this algorithm a mutiple banks architecture for memory is proposed, with every bank constituted by single port srams on the chip. Comparing with other systems for perspective transformation which usually use dual port sram, this architecture comprised of single port sram Greatly reduce the memory area and cost with no sacrifice in calculation speed. In addition, for coordinate calculation this paper specially suggests a struture, reducing the hardware cost while improve the speed. Also the architecture support the parametric design which allows ASIC extending design for different image size and pixel width.In digital circuit function simulation, processing time for a 512*512 gray level image by this architecture is 3.78ms(clock frequency is 100MHz). Output data rate is76.4Mpixel/s, which fulfills real-time demand for most image processing systems.