Study On Architecture Optimization Of Dual-Standard High-Defination Video Encoder ASIC Design

The second-generation video coding standards H.264/AVC and AVS, based on the hybrid video coding framework, achieve high efficient compression as well as increase the complexity of design and implementation inevitably. With the increasing of High Definition (HD) video applications and development of VLSI, the HD video encoder chip supporting H.264/AVC and AVS, is necessary and feasible.The way to make products successful is to achieve high-performance, low-cost, low-power-consumption and short-time design, which are also the quality index and optimization purposes for chip design. This thesis first explores popular optimization methods in chip design, based on the reconfigaurable video coding then propose special strategies for dual standard video encoder optimization such as hierarchical function unit design, different kinds of data connection, three control methods and renconfigurable function unit design, and then focuses on the system, intra mode decision and in-loop deblocking filter design and optimization of the HD video encoder chip supporting H.264/AVC High Profile and AVS Jiaqiang Profile.In the encoder system design, we firstly choose the suitable coding arithmetics according design objects and constraints, and then adopt balanced 4-macroblock-stage pipeline architecture, hierarchical function unit design, several different function unit connections and hierarchical and reused controls, which make our design can achieve real-time encoding of high definition 1920x1080 videos, reuse in H.264/AVC and AVS and some extensibility.In the non-specified intra mode decision, we choose the suitable arithmetics to balance performance and cost, and then make low level function unit partition to enhance the extensibility. Finally the reuse exploring in the data access and prediction architecture, minimum parallel, multilevel pipeline design and separate controlling make our design higher process speed and lower area cost.In the standard-specified in-loop deblocking filter, a new filter order which reduces the buffer size and ram port is proposed for memory resource optimization, the reuse in such as filters, filter condition calculation and time control between the dual standard is explored which makes our design reconfigurable as well as reduces the logic resource consumption.