Research On The Architecture And VLSI Implementation Of The FFT Processor For The On-board Real-time SAR Imaging Processing

In this paper,we research the design and VLSI implementation of the FFT processor according to the demand of the real-time processing of on-orbit SAR data.It is studied from three aspects:the FFT processor structure,the FFT processor data format and the cooperative operation of the FFT processor in a real-time data processing system.The main contents and innovations of the thesis include the following aspects:1.For a multi-channel SAR echo processing requirement,we propose a variable length,mixed-radix and parallel pipelined structure FFT processor.By analyzing the number of channels and the FFT algorithm of each channel,the balanced number of multipliers is achieved to avoid that the number of operation units is doubled by the number of the parallel channels.Combining the radix-2/3/4 multiplexing butterfly unit and the variable length FFT design of each single channel,it is flexible to adapt to 2^k-and 3*2^3k-points FFT processing.In addition,the constant factor multipliers and the sharing twiddle factor lookup table of the parallel channels further reduce the hardware occupation of the FFT processor.For the multi-mode SAR data processing,a variable length,high precision pipelined structure FFT processor is proposed.The FFT processor is designed with the radix-2⁵ FFT algorithm.With the the configurable processing unit(CPE),2048?32768-point FFT can be processed.The configurable constant factor multiplier is designed to realize the variety of constant factors of the radix-2⁵ algorithm.Applying the twiddle factor lookup table division technology,the depth of the twiddle factor lookup table ROM is significantly reduced.Finally,applying the feedback memory re-allocation technology,high-accuracy FFT processing performance can be achieved to the FFT lengths except for 32,768.A generalized method of evaluating the output SQNR of the fixed-point FFT is proposed.The error propagation model of the fixed-point FFT is established accurately based on the matrix representation,and the analytical relationship between the word length and the output quantization noise is derived.Based on the SQNR analytic expression,a fast word length optimization method is proposed.The optimization schemes generated by this method can further save the storage and computing resources of the FFT processor,and make the fixed-point FFT processor more suitable for the harsh hardware resource requirements of the on-orbit processing.Based on the FFT processor structure design and the fixed point theory,a customized pipeline-structured FFT processor ASIC with word length optimization is designed.With FPGA processor,an FPGA-ASIC partially fixed(only FFT operation is proposed to be mixed)system is proposed,and the prototype verification is carried out.While taking advantage of the fixed-point processing,the quantization error effect of the fixed-point system is evaluated quantitatively to ensure that the imaging accuracy is not affected.By analyzing the bandwidth matching relationship of the key nodes of the system,a reasonable mapping strategy is obtained from the SAR imaging algorithm to the hardware system,which makes the prototype system achieve a good compromise between the hardware scale and the processing delay.