Research On Key Techniques Optimization Of Microprocessor Memory Architecture

The advent of big data era has exacerbated the already serious problems of memory wall,bandwidth wall and power wall.It also makes the memory system become the performance bottleneck in the whole computer system when dealing with data-intensive workloads.In recent year,some customized memory optimization techniques,as well as some novel memory architecture and media,has offer the high possibility of the development of memory architecture.This paper is oriented to some real problems in the current memory structure,focusing on the optimization of the memory structure in many levels.In conjunction with the advantage and disadvantage of different memory architecture and hierarchies,some optimization frameworks have been proposed in this paper to migrated the problems and improve the performance.Besides,using the processing-in-memory features of the novel memory architecture,this paper also explores the possibility of using a memory system as an accelerator with a new perspective.Under the current framework of commercial memory architecture and some novel memory concept,this paper focus on three issues: 1)how to fully exploit the potential of the prefetching technology under the current complex multi-level memory hierarchy;2)how to achieve higher effective capacity by compression technology which the DRAM scalability is weak and the capacity of novel memory architecture is not greatly improved;3)how to rationally utilize the logic layer of the current three-dimensional stacked memory architecture for in-memory computing,and accelerate a certain type of workloads.The main contributions of this paper are as follows:1.We proposed a composite hierarchy-aware method for improving the prefetching efficiency of multi-level memory structure,called CHAM(Composite Hierarchy-Aware Method for improving Prefetch Efficiency).Hardware prefetching has always been a significant way to improve system performance.However,the efficiency of hardware prefetching largely depends on the prefetching accuracy.The prefetcher may degrade the performance of the system while the accuracy is low.Previous work has proposed that an adaptive prefetching method for two-level Cache structure.This method can improve system performance in two-level Cache structure,but it does not work well for a more complex memory system,such as a three-level cache structure.CHAM is deployed in the middle level cache(MLC)in the memory system,using the prefetch accuracy in the runtime as the evaluation parameter.CHAM contains two sub-systems: 1)dynamic adaptive prefetch control mechanism to schedule the priority and data transfer of prefetch accesses across the cache hierarchical levels in the runtime and 2)a prefetch efficiency-oriented hybrid cache replacement policy to select the most suitable policy2.We proposed a new strategy to increase the effective data capacity of the HMC,called Compression Management for HMC(CMH,Compression Management in the Hybrid Memory Cube).due to limitations in scalability and power density of a DRAM bit cell,the physical data capacity of an individual HMC is relatively modest and unlikely to grow significantly and it is likely to be a challenge in adopting the HMC for big data in high-performance computing.CMH is deployed in the logic layer of the HMC.By selectively compressing data during data transmission and selectively compressing data stored in the DRAM layer in the HMC,CMH can effectively increase the capacity.It can also save bandwidth consumed in the runtime.3.We proposed two novel mechanisms,HMCSP(CSR-based SPMV in Hybrid Memory Cube)and CGAcc(CSR-based Graph Traversal Accelerator on HMC),to accelerate two classical applications,Matrix Multiplication and Graph Traversal,which have completely different memory access pattern.As a novel of three-dimensional stacked memory structure,HMC stacks DRAM layers,which responsible for storing data,on a logical layer with computational functions.Taking the advantage of the processing in memory(PIM)feature and very short access delays from logical layer to DRAM layer,HMC can be used as an accelerator for optimizing some significant workloads.HMCSP is such a method that use the PIM component on HMC's logic layer to reduce the transaction latency and improving the performance;CGAcc is deployed on the logic layer and uses the inmemory prefetcher to utilize its PIM components.CGAcc can optimize graph traverse by taking advantage of the short transaction delay and parallelizing the prefetch to increase the memory-level parallelism.Optimization of memory system has always been a research hotspot.However,due to the rapid development of memory technology,there is still great space for the memory optimization.This paper designs and presents some optimization techniques and frameworks for improving performance and capacity based on the current general memory architecture and some novel memory concepts.All of the works have been evaluated by comprehensive and sufficient experiments.The results also show that the optimizations of the memory system are practical and can be applied to the design and implementation of future memory systems.