| A 400-MS/s 8-bit high speed SAR ADC is presented in this paper. Compared with traditional 1 bit per cycle SAR ADC, the proposed architecture could produce 2bits per cycle. To implement 2b/cycle SAR ADC, two capacitor arrays are adopted here, including M-DAC and AUX-DAC. M-DAC is used to sample input signal and implement successive approximate logic, while AUX-DAC is used to generate the reference voltages, which are used for comparison to output 2-bit digits. M-DAC adopts top plate sampling, which could reduce a half of the total sampling capacitors, comparing with traditional bottom plate sampling. Besides, because of the advantage of 2b/cycle architecture, the final 2bits could directly output without sending to DAC to settle down, thus the total capacitors could further reduce a half based on the condition above.Therefore, the total capacitor of the proposed structure is only 1/4 of the traditional ones. Moreover, M-DAC adopts split capacitors, which guarantees the common mode voltage of the input signal does not change during the conversion. Additionally, the proposed architecture adopts an interpolation preamplifier to separate the input signal and comparators, which could reduce the kick-back noise. To further increase the conversion speed, the proposed structure adoptsalternative comparators, which means different group of comparators for each cycle.This could greatly simplify the SAR logic circuits, reducing the delay.And the output of the comparators could be directly sent to DAC. Since the proposed architecture use multiple comparators, the offsets of the comparators could significantly affect the performance of the whole system, therefore, digital foreground calibration is used to calibrate the offsets of the comparators.The proposed SAR ADC was taped-out in TSMC 65nm. The effective area is 340μm X 260μm. The post simulation results show that the proposed ADC achieves an SNDR of 48dB, SFDR of 58dB, and consumes 5.6mW, resulting in a figure of merit (FoM) of 67fJ/conversion-step. |
