Research On SSD Flash Tranlation Layer Optimization Algorithm Based On Page Group Mapping

With the rapid development of flash memory technology, the solid state disk becomes more and more popular with characteristics of small size, low power consumption, strong vibration resistance, high reliability. Flash translation layer(FTL) algorithm is one of the key technology of the solid state disk controller, and its performance can directly affect the read and write performance of the solid state disk. There are kinds of FTL algorithms, but these algorithms usually only optimize one aspect of the FTL algorithm, and even the performance improvement of one aspect is at the expense of the performance of another aspect. Therefore, improving the overall performance of the flash translation layer algorithm has great significance to the improvement of solid state disk read and write performance. Based on the analysis of existing flash translation layer algorithms, this paper proposes a flash translation layer optimization algorithm(pg-FTL algorithm) based on page group mapping, and evaluates the algorithm with the method of software simulation and hardware test.Firstly, with studying the basic flash translation layer algorithm, the existing shortcomings of the flash translation layer address mapping algorithm, garbage collection and wear-leveling algorithms are analyzed, and the research focus of designing the flash translation layer algorithm and the overall scheme of the algorithm research are put forward.Secondly, the address mapping algorithm based on page group structure is proposed, and in this algorithm the address mapping table is divided into three levels, channels, page group and page group offset, and it can solve the problem of large mapping table, and at the same time the parallelism between channels can be made use and the parallel operation of multiple requests can be realized. In order to reduce the data migration and garbage collection operations caused by data updating, combining with the characteristic of pg-FTL address mapping algorithm, data update mechanism based on log page group and garbage collection algorithm based on page group threshold are proposed. The static wear-leveling algorithm is optimized in this paper to solve the problem of the unbalance of blocks erasure times of different physical blocks.Thirdly, in order to verify the performance of pg-FTL algorithm, software of the algorithm is designed under the Flashsim simulation environment and the simulation platform is built. Four kinds of real traces on the simulation platform are used to test the performance of pg-FTL algorithm, respectively from SRAM cache hit ratio, average system response time, system response time distribution, read and write performance, block erasure times, GC read and write operation times, and the simulation results are compared with the results of the page address mapping algorithm, FAST algorithm and DFTL algorithm, and the results show that pg-FTL algorithm has superiority in multiple aspects of performance.Finally, on the Jasmine board hardware platform, the general hard disk testing tools Iometer is used to test the sequential read-write speed and 4K random read-write speed of pg-FTL algorithm and the page address mapping algorithm, and the test results show that pg-FTL algorithm has superior performance in sequential read.