The FTL Design Of Flash Memory Based On Virtual Partition Page-Mapping

Over the past few years, the NAND Flash memory has become the preferred storage medium in the embedded system and has also brought a new prospect for the enterprise storage system, because of its absolute advantages in rapid access speed, small volume, impact resistance, non-volatile ability, security and good reliability. However, the existing disk storage technology cannot run directly on the NAND Flash device. So in order to apply the existing disk storage technology on the Flash memory devices, the FTL was introduced into the NAND Flash memory. Therefore, studying high-efficiency FTL is of great importance.The FTL is composed of the following three aspects:address translation, garbage collection and wear-levering. An improved algorithm of FTL is proposed in this paper which is based on the page-level address mapping of DFTL. To reasonably use the SRAM resources and reduce the mapping information storage capacity, a partitioned virtual layer is realized, so that we can use the physical layer with more flexibility. In this paper, first of all, we analyzed and summarized the existing typical FTL algorithms. Secondly, several key technologies which is related to the flash translation layer is introduced, and the address mapping translation, wear-levering and the electric protection are studied. Finally in view of the algorithm designed, we put forward our corresponding solution. The content of this paper mainly includes the following aspects:(1) The basic operating principles of NAND Flash and the implementation of some relative key technologies in Flash memory systems are studied;(2) An address mapping scheme is proposed based on DFTL in this paper. Virtual partitions are constructed according to the size of the storage capacity so that the mapping information capacity can be reduced. At the same time, it can load more mapping entries on the SRAM, improving the system cache hit ratio;(3) Based on the secondary page mapping, we added the index of one translation page, reducing the cost of SRAM. At the same time, a mapping information translation page of the existing working zone can be pre-fetched, which enables the improved algorithm take care of the space locality requests;(4) Through the FlashSim simulation platform, we simulated the algorithm and make a comparison with FAST and DFTL.According to the tests under different working loads, our FTL algorithm based on partitioned virtual layer has obvious advantages compared with several other algorithms.