Research Of A Subpage-based FTL Performance Optimized Algorithm In Solid State Storage

Solid State Disks(SSDs) upgrade a lot in read and write latency, bandwidth, power consumption, reliability and so on, compared with the traditional mechanical hard disk, so that they are applied more widely in currently storage system. In order to obtain larger capacity, reduce the cost per cell and improve the write throughput, flash memory manufacturers aggressively increase the flash page size. However, the size of IO requests within a wide range of the current application scenario do not synchronize. The size discrepancy problem leads to a phenomenon that small random writes become quite common while using flash, which will reduce the performance of flash memory, as well as space utilization and lifetime.To deal with the performance and space utilization problem brought by larger flash page size, this paper propose a new subpage-based FTL algorithm, named Subpage-level FTL(SFTL). SFTL introduce a more flexible subpage mapping layer by making a single flash page divided into smaller units, and convert the I/O requests from upper file system into subpage-level read/write requests. In order to reduce the demand for the SRAM space, SFTL adopt the hybrid mapping idea, using log pages to record the updates occurred on data pages at subpage granularity. Log and data pages are mixed stored in flash memory block. Data pages employ page-level mapping, while log pages employ subpage-level mapping. Under this address mapping scheme, SFTL introduce a garbage collection method based on merging in subpage level which means proceed the merge and recycle operation of log and data pages by page. This paper also propose a LRU data caching and replacement strategy using subpage as manageable node, so as to improve the read/write performance of flash memory.Finally, SFTL is simulated and implemented on a platform called Flashsim. Test results show that SFTL can significantly improve the efficiency of write, and lower the write amplification, resulting in raise flash memory performance and lifetime. Compared with FAST and DFTL, average response time in SFTL reduce up to nearly 82% and 31% respectively; and the number of block erase reduce up to nearly 94% and 46%, respectively.