Research And Design Of Flash Memory Layer For EMMC Storage System

With the appearance of the embedded multi media card(eMMC), the memory card which could hot plug has been replaced. And the eMMC device expands the memory space room, also simplifies the internal design of the mobile phones and the other electronic equipment. In general, the eMMC contains three parts:controller, flash translation layer(FTL) and the array of NAND flash.FTL is the core of the storage device, and it influences the read and write performance and the lifetime of the device. While design the algorithm of FTL, the characteristic of the NAND flash and the protocol layer of eMMC should be took into consideration. The algorithm of FTL can be divided into three mapping method: page-mapping scheme, block-mapping scheme, and hybrid mapping scheme. The page-mapping scheme is the simplest scheme. This scheme sets up the logical page to physical page directly, which is very efficient and flexible. But the disadvantage of the page-mapping scheme is obviously. The higher of the density, the more memory space is needed. The block-mapping scheme is based on the block, so the granularity is bigger than page-mapping scheme, and it will need fewer SRAM room. Compared to the page-mapping scheme, garbage collection is very frequently. It will seriously influence the whole performance of the device. The hybrid mapping scheme absorb the advantage of the page-mapping scheme and block-mapping scheme. It not only keeps the flexibility of update data, but also can^reduce the occupied SRAM room. The above mapping schemes need the frequently garbage collection, so the performance of the garbage collection is very important. In order to reduce the garbage collection and the RAM spare for mapping, this paper proposes the demand-based three level mapping strategy of FTL. The mapping table stored in the NAND flash, and the fewer mapping stored in the SRAM. By the LRU algorithm need to swap the mapping table from the NAND flash to SRAM.A new demand-based three level mapping strategy of FTL was proposed. The DFTL algorithm and the limitation of the DFTL were studied. This paper takes the DFTL for example, and proposes the research of a three-level mapping management flash translation layer on-demands(TFTL). This algorithm does not assign the specific NAND flash blocks for mapping table or user data. The mapping table and user data share all the NAND flash blocks. The platform of FlashSim is set up. And by the platform, we test the veracity and the complexity of the FTL algorithm. The FTL algorithms which are integrated in FlashSim can be used to estimate the performance of the FTL algorithm. And there are five performance indexes to test the TFTL:the system response time, the standard deviation of system response time, the power dissipation, the wear leveling and the count of erased.Considering the limitation of the erase counts, TFTL takes all the NAND Flash blocks to be stored in the NAND table. Once the TFTL allocates one NAND Flash block from the NAND table, we choose the youngest one for user to balance the NAND erase count. Compared to page mapping FTL DFTL and FAST, TFTL has a better performance on the NAND wear leveling, the system response time, and the standard deviation of system response time.