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Research Of A Compressed-page-based FTL Performance Optimized Algorithm In Solid State Storage

Posted on:2019-10-25Degree:MasterType:Thesis
Country:ChinaCandidate:H ChangFull Text:PDF
GTID:2428330563492878Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
Solid-State disk(SSD)is an external storage device with high speed and low latency,and is widely used in the current computer system.Solid-State disks use flash memory chips to store data and manage the chip via the flash translation layer(FTL).With the development of chip manufacturing technology,capacity and page size of chips are increasing,which aggravates the problem of reading and writing granularity mismatch and the writing amplification effect,resulting in the impact of the service life and reading and writing speed.By optimizing the algorithm of the flash translation layer,the problem of read-write granularity mismatch can be improved and the writing amplification can be reduced to improve the service life and reading and writing performance of the hard disk.Compression of page data leads to an effective reduction of data written,improving the write performance and prolong the life expectancy of SSD.A solid state storage FTL performance optimization algorithm based on compressed pages(CPFTL)is therefore proposed.The algorithm uses page level mapping that realizes the support that writing compressed pages,which length is variable,to the fixed-length physical page of NAND Flash by improving the method of flash translation layer.With the design of garbage collection and wear-leveling,the latency of request response and life expectancy are improved.CPFTL algorithm also offers a two-stage caching strategy,which improves the cache hit ratio by distinguishing hot data from cold.These strategies reduce the amount of physical data written,improve the life expectancy of flash memory chip and read-write performance,solve the problem that the granularity mismatch of the read and write requests,thus lead to a huge improvement of the overall performance.The simulation results show that the CPFTL algorithm reduces the write amplification by 87.94% when the average compression rate is 56.25%,and the time required to complete the request is reduced by 85.45%,which effectively reduces the amount of data writing and the response latency.
Keywords/Search Tags:Flash Translation Layer, Compressed-Page, Solid State Disk, Address Mapping, Write Amplification
PDF Full Text Request
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