The Optimization And Verification Of JPEG2000 Codec

JPEG2000 still image compression standard adopted lifting-based DWT(Discrete Wavelet Transform)algorithm and EBCOT(Embedded Block Coding with Optimized Truncation)algorithm to obtain higher performance compared with JPEG standard. While compute-intensive DWT algorithm and bit-based EBCOT algorithm specially and urgently need hardware speedup.The code and decode process in JPEG2000 would be optimized using similar strategy. Focused on the lifting scheme of DWT/IDWT algorithm, this paper derived a transformed formula and strictly designed data flow as a transition to the pipeline structure realization. In EBCOT algorithm, especially for bit-plane scanning algorithm, three passes are under uniform treatment to reduce hardware consumption, the process of stripe-column and the generation of context window are under a piped way to shorten clock cycle. As for MQ algorithm, the logic reorganization extremely simplified the critical path, and the prediction of left-shift times in renormalization procedure greatly decrease cycle time. Considering tag-tree algorithm in Tier-2, the parity tag for row and column, as well as the line buffer indicating whether the father nodes are coded, are utilized to codec size-varied picture. Rate control algorithm is additionally considered in encoder. The last pass of already coded blocks and the current pass are compared to gain the least slope of rate distortion, and selectively bypass the currently coding code-block, therefore lessen the searching time and redundancy coding procedure at the cost of slight loss of image quality compared with PCRD algorithm adopted in JPEG2000.Based on the proposed hardware optimization, RTL model of JPEG2000 hardware codec was described by Verilog HDL language. Using ‘Golden Model’strategy, behavior and timing simulation were accomplished by automatically and successfully comparing the key verification point. The hardware system embedded with JPEG2000 hardware codec logic was then setup in SoC system. FPGA verification including system simulation and software debug were performed afterwardz.The FPGA synthesization results show that the hardware codec can work at 170 M frequency with little hardware consumption. The trade-off between codec time and image quality is perfectly satisfied under 20% compression ratio.