Design Of Chip JPEG2000 And Verification

The image compression standard JPEG2000 was published by the JPEG committee in 2000. It has changed the DCT transform method which the traditional JPEG standard takes as the core, and adopts wavelet transform instead with more concentrated energy and Embedded Block Coding algorithm with Optimized Truncation (EBCOT). JPEG2000 achieves a better compression performance, and supports ROI, SNR-progressive, and a better coding efficiency and image quality that compared with JPEG. In order to obtain a wide application, it has a vital meaning to study the high effective implement of hardware of EBCOT.The EBCOT algorithm consists of two functional parts, a T1 module and T2 module. T1 is responsible for the bit-plane coding and MQ arithmetic coding, and T2 is responsible for the Post Compression Rate Distortion (PCRD) and code-stream ordering. Since high need of internal storage and its complexity, the coding efficiency is the bottleneck of the part T2, which is the key point of design and improvement.The paper states clearly about the code-stream ordering in T2 encoding of the EBCOT algorithm. According to the former research,an improvement approach is pointed out and implemented in Verilog-HDL. In addition, a study on the simulation of T2 module and a new scheme of SRAM accessing are provided to resolve a concealed problem in a former system. It provides a new plan of SRAM read-write which achieves logic synthesizable in ISE 10.1 environment and has a test in FPGA platform at last. The result shows that these efforts indeed simplify the circuits and enhance the frequency of the system. Finally, the Chip based on JPEG2000 is successfully applied in the image compression system.