Parallel Architecture For Ebcot In Jpeg2000, Coding And Fpga Implementation

JPEG2000, a newly proposed image compressing standard, compared with JPEG and other compressing methods, has a better compressing efficiency, providing more powerful functions than others. Therefore, it has wide application whatever in the Internet application, colorful copy, print, scan, medical images and image transmission, and so on.Digital still camera using single-chip CCD or CMOS sensor acquires colorful image with a Color Filter Array (CFA). Based on the analysis of particularity of Bayer pattern, some methods and issues were discussed involving the compression of CFA data before compression. Then, a new chromaticity space measure method and a CZP measure method of image quality are proposed. These methods can highly reflect the differences between performances of the methods and give guidance for selection. Last, a pre-process method is simulated and tested by hardware of FPGA with a simulation wave show.The thesis proposed a high-speed bitplane coder architecture for JPEG2000. Two main methods are proposed to accelerate coding speed: Asynchronous Pipeline Structure and Bitplane Parallel. The former is used successfully to enhance the parallelism within a single Bitplane and resolve efficiently data backlog and data stop caused by the difference of length and the unsurence of length of Pipeline; the later can encode simultaneously all of the Bitplane of wavelet coefficients. Simulation analysis by Quartus II 5.0 shows that the Speed Ratio (SR) for three-step Asynchronous Pipeline can up to 2.86, which can greatly improve processing speed going with Bitplane Parallel. The average strip clock cycle raises 3 times more than "line-based method" when deal with the code block with the size of 32×32×11bit.The thesis proposed a high effeiciency MQ arithmetic coding structure based on the JPEG2000 standard and then had an implement of it. The encoder used optimization algorithm in many places to simplify hardware implementation structure and a three-step Asynchronous Pipeline to advance data processing speed. In the actual state, the Speed Ratio of random signals of the system gets close to 2.25 which are nearly equal to the pipeline segments. The average processing speed can reach to 0.58bit/cycle.Finally, the T-1 part was tested as a whole using SignalTap II logic analyzer software to capture data. The encoder was tested validity according to comparition data between hardware results and the Matlab simulation results. The whole system works at the clock speed at 40MHz and the final results can reach to the speed of 37fps at the serial method and 344fps at the parallel method and is validated correct.