The Optimization And Implementation Of JPEG2000 Codec System

JPEG2000 standard compression algorithm uses discrete wavelet transform(DWT)and optimized truncated embedded block coding(EBCOT)algorithm.Compared with JPEG algorithm,JPEG2000 has many advantages,and is widely used in many areas of image processing in the world.This article analyzes the original IP hardware structure in detail and finds that it is necessary to optimize the area occupied and the resolution of the supported images.In this paper,by analyzing the compression algorithm of the JPEG2000 standard protocol first,using the similarity of the encoding and decoding parts of the algorithm and the inverse of the process,the codec structure is optimized and integrated to realize a hardware structure that can simultaneously have encoding or decoding functions,greatly reducing hardware area.For the overall hardware structure,reuse the wavelet coefficient memory and code stream memory required by the codec,and the overall memory area is reduced by 62%.For the wavelet forward and inverse transform part,different pipeline structures are selected according to the coding or decoding mode,and the memory and logic are multiplexed.For bit-plane scan algorithm,multiplex context generation and other logic and memory resources.For MQ algorithm,multiplex probability estimation logic based on state transition.Then on the basis of the hardware structure optimization,the IP function is further extended.Two schemes are proposed to implement the design of supporting 1024×1024 large-resolution image codec IP.The scheme one adopts‘splicing method'to divide the image into 4 dimensions of 512×512 blocks,the second program to achieve ‘integral optimization design method' to complete.The hardware designs completed by the two schemes have their own advantages and disadvantages.They can be selected and used according to the actual requirements of different scenarios.This paper uses Verilog HDL language to complete the hardware code implementation for the optimized structure.Through full verification and performance analysis of the IP core,it performs well in many aspects such as code coverage,self-consistency,configurable functions,and the highest encoding mode.The operating frequency can reach close to 150 MHz,and the maximum operating frequency of the decoding mode can exceed 175 MHz,meeting the actual codec requirements.This article uses Xilinx tools to build the So C system,and builds a system-level verification platform based on FPGA,which can realize complete coding or decoding function.The decoded image can be displayed on the monitor when decoding,and the design function is verified.