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Research And Application Of Convolutional And Low-Density Parity-Check Codes

Posted on:2008-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:X Y SunFull Text:PDF
GTID:2178360272977927Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
From the point of practical application, this thesis deeply analyzes the encoding and decoding principle of Convolutional and Low-Density Parity-Check (LDPC) codes. Through the studies of encoding and decoding algorithms deeply, the circuits which adapted to FPGA implementation are designed, which can get the good tradeoff between the performance and the complexity. The main results of the work are as follows:(1) Based on IEEE 802.11a standard, a new scheme of decoder is designed and implemented. The diagrams and numerical values of metrics in soft decision de-mapping for this standard are deduced. A parallel adding-zero scheme is proposed, which reduces the highest requirement of the working clock. A completely parallel Viterbi decoder with good performance is designed, which adopts 1_norm to replace Euclidean distance as soft decision distance and uses a new parallel comparison module which could assemble a kind of status information simultaneously. The decoder can process the data at 54Mbits/s by using the working clock frequency not more than 72MHz, which can satisfy the multi-mode requirement of the system.(2) According to GB20600-2006 standard, the encoder with multi-mode for inside code (QC-LDPC: Quasi-Cyclic Low-Density Parity-Check code) is designed. The two kinds of key circuits by using shift-register are implemented corresponding to the two encoding methods for QC-LDPC. Furthermore the complexities of two methods are compared. The encoder adopting the row encoding method is designed and implemented by FPGA.(3) From the view of circuit realization, the decoding algorithms for LDPC are researched. Three numerically accurate representations of the check-node update computation used in log-likelihood-ratio-based belief-propagation (LLR-BP) decoding are described. The relationship of belief-propagation (BP) and min-sum (MS) algorithms is elicited. Two min-sum algorithms which is called normalization min-sum (NMS) and offset min-sum (OMS) are discussed. Simulation results show that: the NMS-OMS decoding algorithm not only gets the merits of reduced-complexity but also achieves a good performance very close to that of the BP algorithm, thus it is a decoding algorithm of significant practicability.
Keywords/Search Tags:Viterbi decoder, low-density parity-check(LDPC) codes, FPGA, belief-propagation (BP) algorithm, min-sum (MS) algorithm
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