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Study On Encoding Of Low Density Parity Check Code

Posted on:2007-07-11Degree:MasterType:Thesis
Country:ChinaCandidate:C Y HaFull Text:PDF
GTID:2178360185485836Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
LDPC (Low Density Parity Check) code is a kind of linear block code that defined by very sparse parity matrix or tanner graph, and it is also called Gallager code since Gallager initially presented it. LDPC code were rediscovered and shown to form a class of Shannon-limit-approaching codes in the late 1990s. These codes, decoded with iterative decoding based on belief propagation, such as the sum-product algorithm, achieve amazingly good error performance. Ever since their rediscovery, design, construction, decoding, efficient encoding, performance analysis, and applications of these codes in digital communication and storage systems have become the focal points of research.LDPC code belongs to the linear block code which is encoded by the information sequence multiplies generator matrix. Although the parity-check matrix of LDPC code is sparse, the generator matrix is not. The encoding complexity of it is linearly proportional to the square of code length. The code length is very large when it be used. Also, a significant amount of memory is needed to store their parity-check matrices. In this way, the encoding problem of LDPC codes may be an obstacle for their applications because they have high encoding complexity. This paper mainly studies encoding problem of LDPC codes.Firstly, the paper introduces the fundamental principle of LDPC code, including LDPC code's basic conception, construction, encoding and decoding algorithm. Then discusses conventional encoding and efficient encoding using special sparse parity check matrix in encoding algorithm, and expatiates the principle of Message Passing and SPA which has the best performance in decoding algorithm.Secondly, the encoder circuit of quasi-cyclic which can realize low encoding complexity are designed and implemented. Three encoder circuit are designed respectively with feed shift-registers and logic gates: SRAA-based serial QC-LDPC encoder; SRAA-based parallel QC-LDPC encoder; two-stage QC-LDPC encoder. It is shown that the encoding complexity of a QC-LDPC code is linearly proportional to the number of parity bits of the code for serial encoding, and to the length of the code for high-speed parallel encoding.
Keywords/Search Tags:quasi-cyclic(QC) LDPC codes, the encoding implementation, sparse parity check matrix, circulant, feedback shift-register
PDF Full Text Request
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