Optimazation And Design For FPGA Circuits Of CBCT Image Reconstruction Based On Row Data Storage

Helical Cone-beam Computed Tomography has been playing an important role in radiation therapy, it has nurished medicine condition and life quality immensely. The key technology of CBCT depends on algotithm model of 3D image section reconstruction, which is a foundation for the entire CT system.After decades’ evolution, the most widely used algorithm now is a kind of exact model based on filtered back-projection proposed by Katsevich in 2002. Because of the vast calculation quantity of the Katsevich algorithm, in this dissertation, to accelerate the process of image reconstruction and decrease chip area effectively, a kind of optimization method based on "row data storage" is presented, and an FPGA acceleration system is developed according to it.Based on "row data storage", details of optimization methods are deduced and analyzed, which avoid the disadvantage that BRAM is consumed too much when an entire frame of data are need to be sotred on chip with a larger resolution of detector. Instead, the new method needs to store only a row of data temporarily. After being read by subsequent module, the row of data can be refreshed then. Under this situation, the cost of BRAM is decreased from one frame to only one row, and the utilization of BRAM is increased as well. To cooperate with this new method, the back rebinning and back-projection steps of Katsevich are optimized as well, both of which are combined into only one module, where a kind of high efficient pipe-line circuit is implemented for them. As a result, hardware cost is decreased to some degree. By this way, the back-projection module reads results from DHT directly, preventing row address conflicts when results of back rebinning and DHT are both stored by rows. In addition, high performance 128 bit PCIe bus transaction level user logic circuits are developed in FPGA as well to connect hardware and software in system, which realize TLP receiving and decoding, coding and tresmitting. The data bandwidth of transaction level in this dissertation reaches up to 250 MHz×128 bit=32 Gb/s, doubling the performance of the 64 bit version.It is shown that it takes 4.57 s by an Intel Core i7-3770 CPU@3.4 GHz to reconstruct a 512×512 section image in field of view, and correspondingly it takes only 0.37 s by the proposed accelarating system, which spends less than 10% of time.