Research Of Interconnect And Memory In Reconfigurable Computing

Reconfigurable computing is emerging as the new paradigm for satisfying the simultaneous demand for application performance and flexibility. Reconfigurable computing is more efficient than pure software mode based on micro-processor, and is more flexible and universal than hardware mode based on hard-wire ASIC. It can provide computing efficiency of hardware and programming property of software.Reconfigurable array is the main body of reconfigurable computing system, which completes certain algorithm task according to its configuration information. Interconnect estimation is important for the design of such array, and its result makes it possible to decrease the wire area as much as possible, In configurable computing system, reconfigurable array interchange data with main memory via data buffer and configuration buffer, and whether this memory architecture is effective affects the performance of the entire computing system.A new stochastic model for reconfigurable array is presented, and it makes it possible to estimate and optimize the required interconnects resource at the beginning of the design work. Based on several statistical assumptions proposed by previous research work, we derive closed formula of probability and mathematical expectation for each type of connections. Both the theoretical deduction and simulation results are given to verify our approach.Optimized memory architecture can accelerate the computing in reconfigurable system, and the evaluation of such architecture requires the analysis of its formal model. Each concrete algorithm is needed to be compiled and divided into task flow graph which is suitable fro reconfigurable computing. The analysis of the parameters of each node task in the flow graph facilitates the evaluation for the performance of reconfigurable computing system.