Research On Multimedia Signal Processing Oriented Operator-based Reconfigurable Cell Circuit

As a new paradigm for current high performance hardware system, reconfigurable hardware promises an intermediate trade-off between ASIC and general purpose microprocessors. Based on software programming, general purpose micorprocessors can't achieve very high computing speed; ASIC has high speed but with disadvantages of fixed architecture and no programmability. Because of its excellent performance and flexibility, reconfigurable hardware has a vast design space and developes quickly. Nowadays, the design of reconfigurable hardware system for application specific domain is a research focus and this thesis emphasizes on multimedia signal processing oriented general hardware architecture and its reconfigurable cell circuit.The main research work of this thesis includes:(1)After analyzing a large number of multimedia signal-processing algorithms, multimedia signal-processing"operators"(multiply-add/subtract or multiply accumulation) are extracted. how to map the common multimedia signal processing algorithms on the multimedia operators is also analyzed.(2)Aiming at multimedia signal processing, the general architecture of a new circuit array FPMACA is presented. A new design scheme of coarse-grain reconfigurable cell circuit PMAC is proposed corresponding to the operators and all the circuit modules of the PMAC are designed in great details. A new reconfigurable 16/8bit BOOTH multiplier is also presented and designed in the thesis.(3)By the simulation, the PMAC and all of its modules are analyzed and verified. At last, the general multimedia signal processing operators of FFT butterfly operation and 4th order FIR filter are implemented on the PMACs, the results show the validity and reliability of PMAC.