Optimal Design Of 16Gb/s VCSEL Driver

With the proliferation of the Internet and the increase of the communication rate, conventional communication network is meeting with the bottleneck. Fiber communication network has gotten a lot of attention due to the large channel volume, well secrecy and anti-jamming capability. The Vertical Cavity Surface Emitting Laser (VCSEL) has the advantage of easy to fabricate 2-D array to realize parallel communication with low driving current, it makes it be used widely.The VCSEL driver circuit designed in this thesis including limiting amplifier, driver circuit and DAC. Basic differential structure is used by the limiting amplifier to realize amplification and limiting function. The pre-emphasis technology is adopted in the driver circuit part to compensate the ringing caused by the bound-wire inductance, pad capacitance and the VCSEL. It gives a better eye-opening and less peak-to-peak jitter. A new method is adopted to optimize the compensation circuit based on the pre-emphasis technology in this thesis. The ringing is eliminated by putting it align with the inverted ringing generated by the compensation signals. The peak-to-peak jitter is reduced dramatically. Single-ended output asymmetric topology is used in the driver circuit to reduce power consumption.This thesis used DACs to adjust the modulation and bias current. The effect caused by the offset voltage of the OPA is considered in the band-gap reference, which can de reduced by increasing the proportion of the triodes. The reference current is produced by the reference voltage and an external resistor, this can avoid the error caused by the change of the internal resistor in different corners. The size of the current source in the DAC is selected through Monte-Carlo simulation, because the leak current will increase if it is too large while the random error will increase if it is too small.The implementation of the VCSEL driver circuit, design of the layout and results of post-simulation are introduced in this thesis. The results of the Monte-Carlo simulation demonstrate that the INL of the DAC is less than 1LSB and the three times of the mean square deviation of the reference voltage is 7.8mV. The results of post simulation demonstrate that good eye opening and a peak-to-peak jitter less than 3ps can be attained. The design adopts TSMC 65nm CMOS technology. The total power consumption is less than 70mW with IV and 3.3V power supplies.