Design And Implementation Of Time-To-Digital Converter In 0.18μm CMOS Technology

With the development of integrated circuit technique, an increasing number of digital circuits are taken as auxiliary units in the design of analog and mixed-signal circuits, such as calibration circuits in ADCs. In addition, ADPLLs are entirely composed of digital units. Digital integrated circuits are good at processing time domain signals. Hence, TDC is widely used in the design of analog and mixed-signal circuits, which acts as a bridge between continuous-time signals and discrete signals. Furthermore, TDC also plays an important role in high energy and particle physicals. So the research on TDCs is meaningful both for high precision measurement and IC design.This thesis mainly studies the high-speed-high-accuracy TDC, the chip is fulfilled with both full-custom and semi-custom methods, which is realized in TSMC 0.18μm CMOS technology. This proposed TDC is composed of three parts:Vernier delay line, readout circuit and encoder circuit. Based on a two-channel Vernier delay line structure and an asynchronous pipelined readout circuitry, the TDC can achieve a maximum throughput of 500MS/s, a time resolution of 10ps and a total conversion range of 640ps. The delay of Vernier delay line must be adapted precisely so the full-custom method is adopted and the others with semi-custom method to decrease the design time and complexity.A test block circuit is embedded in the TDC to generate different time interval to facilitate the measurement. The TDC has been taped out with a total area including I/O pads of 1.25×0.675mm2. Test results show that the proposed TDC basically reach the demand of designed specification. And the average current of the TDC is 66.2mA when power supply voltage is 1.8 V and frequency of the input signal is 500MHz.In order to improve the performance of TDCs, some calibrating methods of Vernier TDC are studied. And the performance of TDC is improved by decreasing the length of single delay line, which is composed of a low-precision TDC and four high-precision TDCs. The total layout area of the new TDC is 0.735×0.92mm2, which is about 80 percent of the previous one. Simulation results show that the improved TDC work correctly.