Research On LDPC Codes For Relay Communication Systems Based On The PEG Algorithm

Since Shannon proposed channel coding theorem, the coding researchers keep looking for channel coding scheme of performance as close as possible to Shannon limit and low complexity and easy implementation. From the early cyclic code, BCH code, RS code and convolution code, cascade code to the development the Turbo code and Low Density Parity Check code(LDPC code) in recent years, the system performance is getting closer and closer to Shannon limit. Because of flexible design, simple decoding and capacity close to Shannon limit and other excellent performance, LDPC code won the wide attention, many high speed data transmission system has been adopted it as a forward error correction technology. This paper regards relay communication of LDPC code and LDPC code decoder hardware structure as the research object, the main content is as follows:The first chapter is the introduction part, the paper introduces the basic knowledge of digital communication system, through the error correction code technology which leads to the LDPC code in channel coding.The second chapter introduced the basic knowledge of the LDPC code, such as its representation method, construction method and encoding scheme, we also introduced the IEEE802.16 e standard method of LDPC codes.The third chapter introduced several decoding algorithms of LDPC code and these decoding algorithms are simulated, and decoding performance can be seen from the simulation results of different algorithms. This chapter is mainly based on the BP decoding algorithm, through the optimization and simplification of BP algorithm, it is concluded that the logarithmic likelihood ratio(LLR) BP decoding algorithm and the minimum sum(Min-Sum) decoding algorithm. Some other optimization algorithm is also introduced in the paper.The fourth chapter introduces the relay communication system as well as traditional PEG algorithm. On the basis of previous studies, we integrally constructed LDPC check matrix using the improved PEG algorithm, increasing the girth of check matrix and improving the performance of error correction.The fifth chapter selects the Min-Sum decoding algorithm as the research object in the hardware design. Using the common top-down design method on LDPC decoder design, and giving the block diagram and each function module is implemented, using ISE 14.7 and Matlab software making logic synthesis and simulation for each function module of LDPC code and top-level module decoder. In this paper, the simulation platform for Xilinx company Nexys3 Spartan-6 FPGA development board.Finally, we summarize the content we have done, and the future research work needs to be introduced briefly.