The Research Of Device And Model For Triple RESURF LDMOS With N-top Layer

Modern power electronics technology requires power devices with superior performance in high voltage, high speed and low loss. The lateral double-diffused MOSFET（LDMOS） is generally used as the switching device which is required a high breakdown voltage（BV） and a low specific on-resistance(R_on,sp) to satisfy the current demand in various high-voltage applications. Triple RESURF technology is beneficial to optimization of the tradeoff between the BV and R_on,sp. The paper is based on a triple RESURF LDMOS structure with n-type top（n-top） layer which can achieve a lower R_on,sp while maintaining the same BV compared with the conventional triple RESURF LDMOS due to the incorporation of the high doped n-top layer.In this paper, two analytical models for the triple RESURF LDMOS with n-top layer is proposed. These analytical models consist of a model for bulk silicon device and a model for SOI device. By solving the 2-D Poisson’s equation, the analytical model for surface potential and electric field distributions is presented and the breakdown voltage is formulized to quantify the breakdown characteristic. Besides, the optimal maximum integrated charge of the n-top layer is derived which can give guidance for the designer to achieve a lowest R_on,sp in the high BV level. All the analytical model results can be well verified by numerical and measured results, showing the validity of the presented models.Besides, based on the triple RESURF LDMOS structure with n-top layer, the substrate termination structure is designed. The key parameters for the transition region is experimentally designed to avoid premature breakdown and the influence of each parameters are analyzed. The new EMMI photo shows that the breakdown point transfers from transitional region to surface straight region. The problem of charge imbalance is solved and the more optimal BV is obtained.What is more, an analytical silicon limit between the R_on,sp and BV for the triple RESURF LDMOS with n-top layer is proposed. R_on,sp =5.93×10^-6×20×BV2 is obtained which demonstrates the proposed triple RESURF LDMOS can break other 1-D RESURF silicon limits and achieve a progressive performance. The analytical model between R_on,sp and BV for the triple RESURF LDMOS with n-top layer shows an excellent match with the simulated results, demonstrating the validity of the proposed model. As expected, this technique has experimentally demonstrated the device performance with a R_on,sp of 87.4 mΩ?cm² at a BV of 796 V which is best-in-class R_on,sp in the published data when D_ntop = 0.8×1012 cm^-2, Ld = 67 μm. The proposed LDMOS demonstrates a progressive performance with lowest R_on,sp in the 700-800 V families and highest FOM of 7.25 MW/cm² in comparison to the other latest existing experimental technologies.