Design And Key Technologies Of Novel Power MOSFET Breaking The Silicon Limit

As the core device of high-efficiency power conversion,power semiconductor devices are the key technology for energy saving and emission reduction.Driven by the development of the global green energy industry,the demand for high-performance power devices in the market sectors such as new energy automobiles,smart appliances,and military products continues to increase.Although the requirements for power semiconductor technology vary from application to application,from the perspective of its development trend,the goal of power semiconductor technology development is always to improve the efficiency of power conversion,to increase the function of the system,and to reduce the size of the system.This article focuses on improving the breakdown voltage?BV?and reducing the conduction loss of the power devices.A series of work on new power MOSFET?Metal-Oxide-Semiconductor Field-Effect Transistor?design,device simulation optimization,device modeling analysis,experimental implementation,and characterization is carried out.By adopting new structures,new materials,new processes and other technologies to improve the performance of new power MOSFET,optimize the contradiction between the BV and specific-on resistance(R_ON,sp)of the device,and break the silicon limit relationship of traditional power MOSFET or Superjunction?SJ?MOSFET.Master the key technologies of high-performance,low-power new power semiconductor devices with independent intellectual property rights.In this paper,two types of new power MOSFETs are proposed by means of electric field modulation,majority carrier accumulation,and trench technology.One is SIPOS MOSFET using semi-insulating polycrystalline silicon?SIPOS?technology;the other is an SJ-LDMOS using a bulk electric field modulation technique.The model analysis is performed on the complete 3D-RESURF?Reduced Surface Field?LDMOS and the body electric field modulation SJ-LDMOS,and the complete 3D-RESURF LDMOS is also verified by the experimental implementation.The main innovations are as follows:?1?A new SJ-LDMOS with SIPOS field plate is proposed.The electric field of the surface of the SJ drift region is uniformly modulated by the SIPOS field plate so that the SJ-LDMOS achieves the complete 3D-RESURF effect.Under the electric field modulation of the SIPOS field plate,the electric field peak at both ends of the drift region is reduced,the electric field in the middle is increased,the electric field distribution on the drift region becomes very uniform,and a high BV is obtained.At the same time,the SIPOS field plate not only increases the doping concentration of the N-buffer layer but also forms a majority carrier accumulation layer at the surface of the SJ,which effectively reduces the on-resistance of SIPOS SJ-LDMOS.The performance of the device is improved by the complete 3D-RESURF effect,and the trade-off between BV and R_ON,sp breaks through the silicon limit.?2?Two new devices,SIPOS UMOS,and SIPOS SJ-UMOS,with longitudinal SIPOS field plates,are proposed.The electric field modulation of the vertical SIPOS field plate effectively reduces the peak electric field at the bottom corner of the trench gate of UMOS and optimizes the overall electric field distribution on the drift region.And for the SJ UMOS device,the SIPOS field plate weakens the peak electric field between the N-pillar and the P-pillar,so that the device can further increase the doping concentration of the N-pillar under a certain BV,thereby reducing the on-resistance of the device.The advantages of electric field modulation and majority carrier accumulation make the two devices not only improve BV but also significantly reduce R_ON,sp.The SIPOS UMOS and SIPOS SJ-UMOS devices break the traditional VDMOS silicon limit and the SJ-VDMOS silicon limit,respectively.?3?Two new devices,MFBL?Multi Floating Buried Layer?SJ-LDMOS,and HK?High K Dielectric Constant Material?SJ-LDMOS,are proposed using body electric field modulation technology.The MFBL and the HK trench as two different body termination technologies,the peak electric field generated by the column junction curvature of the N⁺drain region of the SJ-LDMOS is effectively reduced.At the same time,the vertical electric field distributions of the device are greatly improved.This increases the vertical depletion depth of the SJ-LDMOS,which also increases the BV.It effectively solves the problem that as the length of the drift region increases,the BV is prone to saturation due to the unoptimized vertical electric field of the SJ-LDMOS.?4?According to the structural characteristics of MFBL SJ-LDMOS,combined with device simulation analysis and closure formula derivation,the vertical potential and electric field distributions of MFBL SJ-LDMOS under the electric field modulation of MFBL are obtained.The physical mechanism of electric field modulation of MFBL is illustrated by a theoretical mathematical model.At the same time,the optimal design of the MFBL structure parameters is illustrated by the mathematical formula.Finally,the theoretical mathematical model is verified by the results of device simulation.?5?For the FSLDMOS?Fold Silicon LDMOS?,combined with simulation analysis and closure formula derivation,a new relationship model between the BV and R_ON,sp of FSLDMOS is established,which breaks through the traditional SJ-LDMOS silicon limit.The mathematical model is used to clarify the physical mechanism of the complete 3D-RESURF for FSLDMOS coved by the SIPOS field plate.These mechanisms include:When the device is turned off,the BV can be improved by the electric field modulation in the drift region by the SIPOS field plate.The SIPOS field plate on the folded drift region is equivalent to a plate capacitance to increase the doping concentration of the device drift region;When the device is turned on,the SIPOS field plate forms a majority carrier accumulation layer on the surface of the drift region to reduce the on-resistance of the device.The folded drift region is equivalent to a widened conductive path to reduce the on-resistance of the device.?6?Experimental verification for the complete 3D-RESURF LDMOS.Firstly,the key process conditions of device fabrication are obtained by process simulation,and then the device layout is drawn and the mask is prepared in accordance with the structural characteristics of the complete 3D-RESURF LDMOS and the 0.35?m BCD process design rule.After several times of single-step key process groping correction,a final round of process flow is used to obtain device samples.The device sample test results show that the device achieves very low R_ON,sp at a certain BV,breaking the traditional SJ-LDMOS limit relationship and verifying the model based on the complete 3D-RESURF LDMOS.In this paper,six new power MOSFETs are proposed.Compared with traditional MOSFET,the contradiction between BV and R_ON,sp of these devices is effectively improved.Through device simulation,model analysis,experimental implementation and characterization,the proposed new device has superior performance,breaks through the traditional silicon limit and SJ silicon limit relationship,which meets the development requirements of energy-saving high-efficiency low-power power MOSFET,and has broad application prospects.