Design And Research Of PLDMOS Based On RESURF Technology

Lateral MOS(Metal Oxide Semiconductor)devices are considered as the main power devices in the integrated circuits.Lateral MOS devices can be divided into nLDMOS(n-channel Lateral Double-diffused MOS)and pLDMOS(p-channel LDMOS)according to the channel doping type.The conventional pLDMOS doesn't have a RESURF(REduced SURface Field)effect due to the same doping type of the substrate and the drift region,so the device has a very low breakdown voltage(BV).Meanwhile,because the mobility of the holes which are the majority carriers of the pLDMOS is low,the Ron,sp(specific on-Resistance)is high.Therefore,the conventional pLDMOS device has a serious relationship between the BV and Ron,sp.In this paper,two new pLDMOS devices with dielectric trench and no dielectric trench are designed based on technologies such as RESURF and ENDIF(ENhanced DIelectric Field).And then,their structural characteristics and mechanism are studied.Not only the problem that the Con.pLDMOS has no RESURF effect is solved,but also the contradiction between the BV and Ron,sp is alleviated.(1)NBL PSOI pLDMOS(N-Buried Layer Partial Silicon On Insulator pLDMOS)structure is proposed.One of the structural features is the introduction of an n-type buried layer(NBL)in the p-type drift region.The NBL can assist deplete the drift region and increase the concentration of the drift region.In the off-state,the fully depleted NBL increases the amount of ionized donor ions for the BOX(Buried Oxide Layer)to increase the electric field of the BOX,which can increase the bV.In the on-state,the Ron,sp decreases because the concentration of the drift region is greatly increased.Simultaneously,the device produces RESURF effect due to the presence of the NBL.Another feature is that there is a silicon window.The presence of the silicon window causes the substrate to participate in depletion,and the BV is further improved.The silicon window can alleviate the self-heating effect(SHE)of the device.The simulation results by Medici show that the NBL PSOI pLDMOS has a BV of 289V,a Ron,sp of 50.6m?·cm2,and the figure of merit(FOM=BV2/Ron,sp)of 1.65MW·cm-2.And the maximum surface temperature(Tmax)is 312.3K.Finally,the process design and layout design of the NBL PSOI pLDMOS device are completed.(2)N-region VFP LK pLDMOS(N-region Vertical Field Plate Low k pLDMOS)is proposed.The structure has three characteristics:N-region,vertical field plate(VFP),and low-k dielectric trench.The N-region is located in the periphery of the p-type drift region,which helps deplete the drift region.So,the device produces RESURF effect.In addition,the VFP introduced in the dielectric trencht can help deplete the drift region and optimize the body electric field to increase the BV of the device.Since the VFP,trench,and left drift region of the trench constitute a MIS(Metal Insulator Semiconductor)structure,a large number of holes are accumulated in the drift region to provide a low current resistance channel.The introduction of low-k dielectric uses ENDIF technology to increase the lateral BV of the device.According to the simulation results of Medici,it is known that the N-region VFP LK pLDMOS obtains a BV of 809V,a Ron,sp of 53.47m?·cm2,and the FOM of 12.24MW·cm-2.Finally,two kinds of process preparation scheme of the new structure are proposed and the layout design is completed.