Frequency Source Design Based On FMCW RADR System

Sampling, is a necessary way to achieve the transformation from analog signal to digital signal, makes it possible to deal with the signal later with computer or other tools. As the development of society and innovation of technology, following with the higher rate of ADC, the high speed sampling system, which the system timing should be more precise, is expected.A good clock source has great importance as footstone of the sampling system; if the clock timing of sampling is a poor performance, it will contribute extra errors to the sample values, so that the following processing after sampling can be precise. Phase jitter is the key indicator of a clock source, which also means phase noise in frequency domain. And a lower phase jitter is the key for a accurate clock source, so a clock source with a lower jitter was designed, which means greatly for my thesis.My thesis, is Based on the project called "high speed sampling system", mainly researches on the jitter of clock coming from clock source. Besides, the frequency of sampling clock is excepted be continuous variable, which means the frequency resolution of sampling clock should be very small in the sampling system.Direct digital frequency synthesis, is called DDS for short, have two obvious advantages: one is frequency agility and the other is that the frequency stepping is very small, which means a high resolution of frequency, but it also have disadvantage just as the saying goes “every coin has two sides”, it brings too many other frequency component which cause a poor performance for the signal of clock outputting, it also means that the spectral purity of clock signal is on poor performance. Therefore, a solution to reduce spectral component was put forward, which can make for the disadvantage of the DDS. In theory, the contribution of clock jitter that phase noise and spur component make, was analyzed; and simulated a modeling with matlab, for I can see how it influence the signal intuitively; besides the solution that put forward which called Spur Killer, can eliminate the spur near the frequency band of the outputting signal which cannot be filtered with a filter, so that the clock jitter can reduce 30 d B to the maximum extent; eventually a clock with low jitter was designed. The main work in this thesis as following.Firstly, in theory the impaction of the phase noise and spurious harmonic to clock jitter is analyzed, then a formula between them was deduced, make it possible to reduce the jitter of clock through the simulation modeling with; later a proposal to remove the worst spur was put forward, and make it feasible in theory.Secondly, a clock source programs with low jitter was designed, and analyze its rationality; and the circuit of AD9912 and its Spur Killer configuration was gave.Thirdly, the performance of clock was test, including its measurements of phase. After configuration of Spur Killer, the jitter is reduced.