Test Of Jitter In Clock Signals

In digital transmission system , jitter is one of the least understood but most important phenomenas . With higher and higher frequency in digital system , the jitter impact is more and more severe. It抯 urgent to measure jitter accurately.In the thesis , the defination of jitter and its impact on the digital systems axe explained. The jitter measuring methods including digital method and analog method are analyzed . Their advantages and disadvantages are compared. Some standards of International Telecomunication Union (ITU) about jitter measuring are presented . Based on all these above , two schemes which use digital methods to measure the jitter of a PLL clock of 2.048MHz are presented and accomplished . The first scheme uses a DSP chip to process the data. And a CPLD (Complicated Programmable Logic Device) is uesed to simplif~r the design. This scheme is easy to accomplish and has relatively high resolution and accuracy . Another digital method of jitter measuring is also presented. Compared with the first one ,this method is easier to accomplish. Its resolution can also satisf~?standards of jitter measuring.